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Computation of sensitivities of IC interconnect parasitic capacitances to the process variation with dual discrete geometric methods

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Journal of Semiconductors 2016年第8期37卷 90-96页

作者：高展任但闫帅徐小宇任卓翔 Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 China University of Chinese Academy of Sciences Beijing 100049 China Beijing Key Laboratory of 3D & Nano IC Electronic Design Automatic Technologies Beijing 100029 China

Sensitivity analysis methods help to deal with the challenges of process variation in extraction of para- sitic capacitances in an integrated circuit. The dual discrete geometric methods （DGMs）, which have been recently utilized to extract parasitic capacitances, are reviewed. The computation method based on the dual DGMs for sen- sitivities of capacitances with respect to the given process parameters is presented. As the dual DGMs utilize scalar electric potential is unknown, the capacitances are obtained effectively, and then the sensitivities are calculated conveniently.

关键词： capacitance extraction dual discrete geometric methods (DGMs) process variation sensitivity ana- lysis

A statistical RCL interconnect delay model taking account of process variations

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Chinese Physics B 2011年第1期20卷 659-666页

作者：朱樟明万达经杨银堂恩云飞 Microelectronics School Xidian University

As the feature size of the CMOS integrated circuit continues to shrink, process variations have become a key factor affecting the interconnect performance. Based on the equivalent Elmore model and the use of the polynomial chaos theory and the Galerkin method, we propose a linear statistical RCL interconnect delay model, taking into account process variations by successive application of the linear approximation method. Based on a variety of nano-CMOS process parameters, HSPICE simulation results show that the maximum error of the proposed model is less than 3.5%. The proposed model is simple, of high precision, and can be used in the analysis and design of nanometer integrated circuit interconnect systems.

关键词： process variation interconnect line statistical delay successive linear approximation

Statistical Interconnect Crosstalk Noise Model and Analysis for process variations

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Chinese Journal of Electronics 2015年第1期24卷 83-87页

作者： LI Jianwei DONG Gang WANG Zeng YE Xiaochun Faculty of Automation and Information Engineering Xi'an University of Technology State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Microelectronics Institute Xidian University College of Physics Sicence Qingdao University

When operating frequency is over several gigahertz, the effect of inductance plays an important role and should be included for accurate and speed crosstalk noise analysis. And for new generation IC(Integrated circuit) design tools, the crosstalk noise analysis tools should consider the influence of process variations. In this paper, we propose coupled RLC crosstalk noise distributed parameter model with capacitive load termination. And we develop the framework that how to use the crosstalk noise model for process variations. Our results show that compare with HSPICE, the critical data errors of proposed model are within 1% and the relative errors occurred between calculated values for process variations and HSPICE Monte Carlo simulation values are less than 5%. The key features of the new model include:(1) The impact of inductance on crosstalk noise is considered;(2) The model can be used for process variations analysis;(3) The model reflect the effects of load capacitance directly;(4) The numerical inversion of Laplace transform is introduced for improving speed. So the proposed model meets the needs of future IC design both in speed and accuracy.

关键词： Crosstalk noise Interconnect Inductance process variation Statistical

The impact of process variations on input impedance and mitigation using a circuit technique in FinFET-based LNA

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Journal of Semiconductors 2015年第4期36卷 104-109页

作者： D.Suresh K.K.Nagarajan R.Srinivasan ECE Department Sri Sivasubramaniya Nadar (SSN) College of Engineering IT Department Sri Sivasubramaniya Nadar (SSN) College of Engineering

The effect of process variations of a FinFET-based low noise amplifier （LNA） are mitigated by using the device in an independently driven mode, i.e. an independently driven double gate （IDDG） FinFET. A 45 nm gate length IDDG FinFET-based cascoded LNA, operating at 5 GHz, is designed and studied to assess the impact of process variation on the LNA performance metrics such as input impedance, gain and noise figure. Four geometrical parameters, gate length, channel width, gate oxide thickness and fin width, and one non-geometrical parameter, channel doping concentration, are considered in the study. The effect of these variations on the input impedance （the desired value is 50 f2 purely real） of the LNA is compensated by the second gate bias of the IDDG FinFET.

关键词： FinFET LNA process variation T-SPICE

Temperature and process variations Aware Dual Threshold Voltage Footed Domino Circuits Leakage Management

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Journal of Semiconductors 2008年第12期29卷 2364-2371页

作者：宫娜汪金辉郭宝增庞娇河北大学电子信息工程学院保定071002 北京工业大学集成电路与系统研究室北京100124

Considering the effect of temperature and process variations, the inputs and clock signals combination sleep state dependent leakage current characteristics is analyzed and the optimal sleep state is examined in sub-65nm dual threshold voltage （V1） footed domino circuits. HSPICE simulations based on 65nm and 45nm BSIM4 models show that the proposed CLIL state （the clock signal and inputs are all low） is the optimal state to reduce the leakage current of the high fan-in footed domino circuits at high temperature and almost all footed domino circuits at room temperature, as compared to the conventional CHIL state （the clock signal is high and inputs are all low） and the CHIH state （the clock signal and inputs are all high）. Further, the influence of the process variations on the leakage current characteristics of the dual V1 footed domino circuits is evaluated. At last, temperature and process variation aware new low leakage current setup guidelines are provided.

关键词： footed domino circuit dual threshold voltage leakage current process variation

Sensitivity Analysis of Effect Related with Material process and Assembly variations to Loads Deformation and Stress on HSS Stamping Die

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Journal of Shanghai Jiaotong university(Science) 2008年第6期13卷 727-733页

作者：张贵宝陈军王晓方 National Die & Mold CAD Engineering Research Center Shanghai Jiaotong UniversityShanghai 200030China Research and Innovation Center Ford Motor CompanyDearborn Michigan 48120 USA

During stamping process, the material properties, process design parameters and production environments inevitably have variation and noisy factors, which possibly affect the sheet metal formability and the deformation of the die *** gaining a success in applying sheet metal forming numerical simulation analysis to get the forming loads during stamping process, a methodology of die structure analysis based on sheet metal forming simulation was proposed and validated by *** on these results, the effect related with initial blank thickness, blank holder force, blank positioning error and die alignment error variations to a DP600 hyperbolic bottomed cup drawing die's forming loads(especially unbalanced loads), and deformation and stress was studied *** influence level of these variations to the die's forming loads, deformation and stress was *** findings can guide die design, die tryout and process control for high-strength steel(HSS) stamping with increased forming load and decreased sheet metal formability.

关键词： sensitivity analysis process variation forming loads die deformation die stress, high-strength steel (HSS) stamping

Analysis and impact of process variability on performance of junctionless double gate VeSFET

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Journal of Semiconductors 2017年第10期38卷 63-69页

作者： T.Chaudhary G.Khanna National Institute of Technology

This paper presents an in-depth analysis of junctionless double gate vertical slit FET（JLDG VeSFET）device under process *** has been observed that junctionless FETs（JLDG VeSFET） are significantly less sensitive to many process parameter variations due to their inherent device structure and geometric *** analysis reveals that the slit width,oxide thickness,radius of the device,gate length and channel doping concentration imperceptibly affect the device performance of JLDG VeSFET in terms of variation in threshold voltage,on current,off current and subthreshold slope（Ssub） as compared to its junction based counterpart ***,because various short channel effects are well controlled in this *** maximum variation in off current for JLDG VeSFET due to variation in different devices parameters is 5.6% whereas this variation is 38.8% for the MOS junction based ***,variation in doping concentration in the channel region displays a small deviation in the threshold voltage and on current characteristics of the MOSFET device as compared to JL DG VeSFET.

关键词： JLDG VeSFET process variation sensitivity scaling short channel effects oxide thickness channel thickness threshold voltage

Comparative Performance Evaluation of Large FPGAs with CNFET-and CMOS-based Switches in Nanoscale

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Nano-Micro Letters 2011年第3期3卷 178-188页

作者： Mohammad Hossein Moaiyeri Ali Jahanian Keivan Navi Faculty of Electrical and Computer Engineering. Shahid Beheshti University G.C. Nanotechnology and Quantum Computing Lab. Shahid Beheshti University G. C. VLSI Design Automation Lab. Shahid Beheshti University G. C.

Routing resources are the major bottlenecks in improving the performance and power consumption of the current FPGAs. Recently reported researches have shown that carbon nanotube field effect transistors(CNFETs) have considerable potentials for improving the delay and power consumption of the modern FPGAs. In this paper, hybrid CNFET-CMOS architecture is presented for FPGAs and then this architecture is evaluated to be used in modern FPGAs. In addition, we have designed and parameterized the CNFET-based FPGA switches and calibrated them for being utilized in FPGAs at 45 nm, 22 nm and 16 nm technology *** results show that the CNFET-based FPGA switches improve the current FPGAs in terms of performance, power consumption and immunity to process and temperature variations. Simulation results and analyses also demonstrate that the performance of the FPGAs is improved about 30%, on average and the average and leakage power consumptions are reduced more than 6% and 98% respectively when the CNFET switches are used instead of MOSFET FPGA switches. Moreover, this technique leads to more than 20.31%smaller area. It is worth mentioning that the advantages of CNFET-based FPGAs are more considerable when the size of FPGAs grows and also when the technology node becomes smaller.

关键词： Carbon nanotube field effect transistor(CNFET) FPGA switches Performance evaluation Power consumption process variation

The study of lithographic variation in resistive random access memory

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Journal of Semiconductors 2024年第5期45卷 69-79页

作者： Yuhang Zhang Guanghui He Feng Zhang Yongfu Li Guoxing Wang Department of Micro-Nano Electronics Shanghai Jiao Tong UniversityShanghai 200240China MoE Key Lab of Artificial Intelligence Shanghai Jiao Tong UniversityShanghai 200240China Institute of Microelectronics Chinese Academy of SciencesBeijing 100029China

Reducing the process variation is a significant concern for resistive random access memory(RRAM).Due to its ultrahigh integration density,RRAM arrays are prone to lithographic variation during the lithography process,introducing electrical variation among different RRAM *** this work,an optical physical verification methodology for the RRAM array is developed,and the effects of different layout parameters on important electrical characteristics are systematically *** results indicate that the RRAM devices can be categorized into three clusters according to their locations and lithography *** read resistance is more sensitive to the locations in the array(~30%)than SET/RESET voltage(variation to less than 10%,whereas it reduces RRAM read resistance by 4×,resulting in a higher power and area *** such,we provide design guidelines to minimize the electrical variation of RRAM arrays due to the lithography process.

关键词： layout lithography process variation resistive random access memory