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High Precision Mix-Signal Capacitor Mismatch Error Calibration Method for Charge-Domain pipelined ADC

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Chinese Journal of Electronics 2019年第2期28卷 223-228页

作者： YU Zongguang ZOU Jiaxuan CHEN Zhenhai WEI Jinghe SU Xiaobo ZHANG Hong School of Microelectronic Xidian University No.58 Research Institute China Electronic Technology Group Corporation School of Information Engineering Huangshan University School of Electronics and Information Engineering Xi'an Jiaotong University

A mix-signal high precision capacitor mismatch error calibration method for charge domain pipelined ADCs is proposed. The calibration method calibrates the capacitors one by one based on binary *** errors caused by the capacitor mismatch in and between pipelined sub-stage circuits can be compensated by the proposed calibration method. Based on the proposed calibration method, a 14 bit 250 MS/s charge domain pipelined analog-to-digital converter（ADC） is designed and realized in a 1P6M 0.18 m CMOS *** results show the 14 bit 250 MS/s ADC achieves the signal-to-noise ratio of 70.7 dBFS and the spurious free dynamic range of 84.6 dB, with 70.1 MHz single-tone sine wave input at 250 MS/s, while the ADC core consumes the power consumption of 235 mW and occupies an area of 3.2 mm;.

关键词： pipelined analog-to-digital converter Charge domain(CD) For-ground calibration Low power Capacitor mismatch

A 12-bit 100 MS/s pipelined ADC with digital background calibration

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Journal of Semiconductors 2009年第11期30卷 109-113页

作者：周立人罗磊叶凡许俊任俊彦 State Key Laboratory of ASIC & System Fudan UniversityMicroelectronics Science and Technology Innovation Platform

This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC） with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter （MDAC） while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18μm CMOS process, occupies an active area of 2.3 × 1.6 mm^2, and consumes 205 mW at 1.8 V.

关键词： pipelined analog-to-digital converter background calibration digital calibration capacitor mismatch finite op-amp gain

A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for IF sampling

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Journal of Semiconductors 2013年第6期34卷 118-125页

作者：陈珍海钱宏文黄嵩人张鸿于宗光 Wide Bandgap Semiconductor Technology Disciplines State Key Laboratory School of MicroelectronicsXidian University China Electronic Technology Group Corporation No.58 Research Institute School of Electronics and Information Engineering Xi'an Jiaotong University

A 10-bit 250-MSPS two-channel time-interleaved charge-domain（CD） pipelined analog-to-digital converter （ADC） is *** bucket-brigade device（BBD） based CD pipelined architecture is used to achieve low power *** all digital low power DLL is used to alleviate the timing mismatches and to reduce the aperture jitter.A new bootstrapped MOS switch is designed in the sample and hold circuit to enhance the IF sampling *** ADC achieves a spurious free dynamic range（SFDR） of 67.1 dB,signal-to-noise ratio （SNDR） of 55.1 dB for a 10.1 MHz input,and SFDR of 61.6 dB,SNDR of 52.6 dB for a 355 MHz input at full sampling *** nonlinearity（DNL） is ＋0.5/-0.4 LSB and integral nonlineariry（INL） is ＋0.8/-0.75 *** in a 0.18-μm 1P6M CMOS process,the prototype 10-bit pipelined ADC occupies 1.8×1.3 mm2 of active die area,and consumes only 68 mW at 1.8 V supply.

关键词： time-interleaved pipelined analog-to-digital converter charge domain low power bootstrapped sampling switch delay locked loop

An 85mW 14-bit 150MS/s pipelined ADC with a Merged First and Second MDAC

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China Communications 2015年第5期12卷 14-21页

作者： LI Weitao LI Fule YANG Changyi LI Shengjing WANG Zhihua Institute of Microelectronics Tsinghua University

A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.

关键词： analog-to-digital conversion lowpower calibration high speed and high reso-lution pipelined analog-to-digital converter CMOS analog integrated circuits

A 27-mW 10-bit 125-MSPS charge domain pipelined ADC with a PVT insensitive boosted charge transfer circuit

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Journal of Semiconductors 2013年第3期34卷 112-120页

作者：陈珍海黄嵩人张鸿于宗光季惠才 Wide Bandgap Semiconductor Technology Disciplines State Key Laboratory School of MicroelectronicsXidian University China Electronic Technology Group Corporation No.58 Research Institute School of Electronics and Information Engineering Xi'an Jiaotong University

A low power 10-bit 125-MSPS charge-domain(CD) pipelined analog-to-digital converter(ADC) based on MOS bucket-brigade devices(BBDs) is presented.A PVT insensitive boosted charge transfer(BCT) that is able to reject the charge error induced by PVT variations is *** the proposed BCT,the common mode charge control circuit can be eliminated in the CD pipelined ADC and the system complexity is reduced *** prototype ADC based on the proposed BCT is realized in a 0.18μm CMOS process,with power consumption of only 27 mW at 1.8-V supply and active die area of 1.04 mm^*** prototype ADC achieves a spurious free dynamic range(SFDR) of 67.7 dB,a signal-to-noise ratio(SNDR) of 57.3 dB,and an effective number of bits(ENOB) of 9.0 for a 3.79 MHz input at full sampling *** measured differential nonlinearity(DNL) and integral nonlinearity (INL) are +0.5/-0.3 LSB and +0.7/-0.55 LSB,respectively.

关键词： pipelined analog-to-digital converter charge domain low power charge transfer circuit charge comparator

SHA-less architecture with enhanced accuracy for pipelined ADC

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Journal of Semiconductors 2012年第2期33卷 117-121页

作者： Zhao Lei Yang Yintang Zhu Zhangming Liu Lianxi School of Microelectronics Xidian UniversityXi’an 710071China

A new design technique for merging the front-end sample-and-hold amplifier（SHA） into the first multiplying digital-to-analog converter（MDAC） is *** reducing the aperture error in the first stage of the pipelined ADC,a symmetrical structure is used in a flash ADC and ***,a variable resistor tuning network is placed at the flash input to compensate for different cutoff frequencies of the input impedances of the flash and *** circuit also has a clear clock phase in the MDAC and separate sampling capacitors in the flash ADC to eliminate the nonlinear charge kickback to the input *** proposed circuit,designed using ASMC 0.35-μm BiCMOS technology,occupies an area of 1.4 x 9 mm^2 and is used as the front-end stage in a 14-bit 125-MS/s pipelined *** the trim circuit is enabled,the measured signal-to-noise ratio is improved from 71.5 to 73.6 dB and the spurious free dynamic range is improved from 80.5 to 83.1 dB with a 30.8 MHz input. The maximum input frequency is up to 150 MHz without steep performance degradations.

关键词： pipelined analog-to-digital converter sample-and-hold amplifier SHA-less aperture error

A 10-bit 250 MSPS charge-domain pipelined ADC with replica controlled PVT insensitive BCT circuit

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Journal of Semiconductors 2015年第5期36卷 163-169页

作者：黄嵩人张鸿陈珍海朱泷于宗光钱宏文郝跃 Wide Bandgap Semiconductor Technology Disciplines State Key Laboratory Xidian University School of Electronics and Information Engineering Xi'an Jiaotong University No.58 Research Institute China Electronic Technology Group Corporation

A low power 10-bit 250 MSPS charge-domain （CD） pipelined analog-to-digital converter （ADC） is introduced. The ADC is implemented in MOS bucket-brigade devices （BBDs） based CD pipelined architecture. A replica controlled boosted charge transfer （BCT） circuit is introduced to reject the influence of PVT variations on the charge transfer process. Based on replica controlled BCT, the CD pipelined ADC is designed and realized in a 1P6M 0.18μm CMOS process. The ADC achieves an SFDR of 64.4 dB, an SNDR of 56.9 dB and an ENOB of 9.2 for a 9.9 MHz input; and an SFDR of 63.1 dB, an SNR of 55.2 dB, an SNDR of 54.5 dB and an ENOB of 8.7 for a 220.5 MHz input at full sampling rate. The DNL is ＋0.5/- 0.55 LSB and INL is ＋0.8/- 0.85 LSB. The power consumption of the prototype ADC is only 45 mW at 1.8 V supply and it occupies an active die area of 1.56 mm2.

关键词： pipelined analog-to-digital converter charge domain low power charge transfer circuit