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Towards high-performance packet processing on commodity multi-cores: current issues and future directions

Science China(Information Sciences) 2015年第12期58卷 28-43页

作者： TANG Lu YAN JinLi SUN ZhiGang LI Tao ZHANG MinXuan School of Computer National University of Defense Technology

The demands of programmability have become more and more exigent as novel network services appear, such as E-commerce, social softwares, and online videos. Commodity multi-core CPUs have been widely applied in network packet processing to get high programmability and reduce the time-to-market. However,there is a great gap between the packet processing performance of commodity multi-core and that of the traditional packet processing hardware, e.g., NP(Network Process). Recently, optimization of the packet processing performance of commodity multi-cores has become a hot topic in industry and academia. In this paper, based on a detailed analysis of the packet processing procedure, firstly we identify two dominating overheads, namely the virtual-to-physical address translation and the packet buffer management. Secondly, we make a comprehensive survey on the current optimization methods. Thirdly, based on the survey, the heterogeneous architecture of the commodity multi-core + FPGA is proposed as a promising way to improve the packet processing ***, a novel Self-Described Buffer(SDB) management technology is introduced to eliminate the overheads of the allocation and deallocation of the packet buffers offloaded to FPGA. Then, an evaluation testbed, named PIOT(packet I/O Testbed), is designed and implemented to evaluate the packet forwarding performance. I/O capacity of different commodity multi-core CPUs and the performance of optimization methods are assessed and compared based on PIOT. At last, the future work of packet processing optimization on multi-core CPUs is discussed.

关键词： network commodity multi-core packet processing SKB DPDK

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A Reconfigurable Hardware Architecture for packet processing

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Chinese Journal of Electronics 2018年第2期27卷 428-432页

作者： DUAN Tong LAN Julong HU Yuxiang LIU Shiran National Digital Switching System & Engineering Technological Research Center

In this paper, we propose a reconfigurable packet processing hardware architecture for future switch,in which several protocol-independent action units are introduced to remove the protocol dependence of conventional packet processors. With the proposed architecture,any specified header fields can be mapped into the right action unit, so that the processor can meet any packet processing demands. To reduce the hardware resource cost,the processor cost model and optimization algorithm are proposed. The Net FPGA-based implementation shows a throughput of 94 Gb/s with 64-B packets. The programmability cost is approximately 1.5 times of conventional design, which consumes only 8% of the total FPGA resources.

关键词： packet processing Hardware architecture Reconfigurable Protocol-independent

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Towards high-performance packet processing on commodity multi-cores: current issues and future directions

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Science China Chemistry 2015年第12期58卷 24-39页

作者： TANG Lu YAN JinLi SUN ZhiGang LI Tao ZHANG MinXuan School of Computer National University of Defense Technology

关键词： network commodity multi-core packet processing SKB DPDK

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An index-split Bloom filter for deep packet inspection

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Science China(Information Sciences) 2011年第1期54卷 23-37页

作者： HUANG Kun1 & ZHANG DaFang1,2 1School of Computer and Communication,Hunan University,Changsha 410082,China 2 School of Software,Hunan University,Changsha 410082,China School of Computer and Communication Hunan University School of Software Hunan University

Deep packet inspection(DPI)scans both packet headers and payloads to search for predefined *** link rates and traffc volumes of Internet are constantly growing,DPI is facing the high performance challenge of how to achieve line-speed packet processing with limited embedded *** recent trie bitmap content analyzer(TriBiCa)suffers from high update overhead and many false positive memory accesses,while the shared-node fast hash table(SFHT)suffers from high update overhead and large memory *** paper presents an index-split Bloom filter(ISBF)to overcome these *** a set of off-chip items,an index of each item is split apart into several groups of constant bits,and each group of bits uses an array of on-chip parallel counting Bloom filters(CBFs)to represent the overall off-chip *** an item is queried,several groups of on-chip parallel CBFs constitute an index of an off-chip item candidate for a ***, we propose a lazy deletion algorithm and vacant insertion algorithm to reduce the update overhead of ISBF, where an on-chip deletion bitmap is used to update on-chip parallel CBFs,not adjusting other related off-chip *** ISBF is a time/space-effcient data structure,which not only achieves O(1)average memory accesses of insertion,deletion,and query,but also reduces the memory *** results demonstrate that compared with the TriBiCa and SFHT,the ISBF significantly reduces the off-chip memory accesses and processing time of primitive operations,as well as both the on-chip and off-chip memory sizes.

关键词： network security packet processing deep packet inspection hash table Bloom filter

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