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A Modified Approach for CMOS Auto-Zeroed Offset-Stabilized opamp

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Circuits and Systems 2013年第2期4卷 193-201页

作者： Abouzar Taghizadeh Ziaddin Daie Koozehkanani Jafar Sobhi Faculty of Electrical and Computer Engineering University of Tabriz Tabriz Iran

In this paper, a very low-offset continuous time amplifier has been presented. It has the fully differential structure and uses an Auto-zeroed offset stabilization technique. This structure consists of two phases in which the offset value is sampled in the first phase and then subtracted from the signal in the second phase. In order to maintain the continuous time topology, the amplifier uses two paths called main-path and sub-path where the main-path is never disconnected from the signal path and as a result the structure will be continuous time. The amplifier is designed to have a total amount of power dissipation about 3 mW in the standard 0.35 μm CMOS process. Furthermore, the proposed opamp has an offset value lower than 1 μV at a 2.5 kHz Auto-zeroing frequency, unity gain frequency of 6.14 MHz and phase margin of 78.6° with 50 pF loads.

关键词： Auto-Zeroing Chopping Offset-Stabilization opamp

A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer

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Journal of Semiconductors 2011年第1期32卷 90-96页

作者：陈奇辉秦亚杰陆波洪志良 State Key Laboratory of ASIC and System Fudan University

A 12-bit 30 MSPS pipeline analog-to-digital converter （ADC） implemented in 0.13μm 1P8M CMOS technology is presented. Low power design with the front-end sample-and-hold amplifier removed is proposed. Except for the first stage, two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption. The ADC presents 65.3 dB SNR, 75.8 dB SFDR and 64.6 dBSNDR at 5 MHz analog input with 30.7 MHz sampling rate. The chip dissipates 33.6 mW from 1.2 V power supply. FOM is 0.79 pJ/conv step.

关键词： analog-to-digital converter pipeline SHA removing opamp on-chip reference buffer

高温6H-SiC CMOS运算放大器的设计

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西北大学学报（自然科学版） 2010年第2期40卷 219-223页

作者：刘莉杨银堂西安电子科技大学宽带隙半导体材料与器件教育部重点实验室陕西西安710071

目的设计可工作在高温下的6H-SiC CMOS运算放大器。方法该电路基于标准的PMOS输入两级运放而成,考虑泄漏电流匹配添加Dcomp二极管。利用零温度系数理论和泄漏电流匹配的原则对电路管子的尺寸进行确定。通过求解SiMOS管和6H-SiC MOS管零... 详细信息

目的设计可工作在高温下的6H-SiC CMOS运算放大器。方法该电路基于标准的PMOS输入两级运放而成,考虑泄漏电流匹配添加Dcomp二极管。利用零温度系数理论和泄漏电流匹配的原则对电路管子的尺寸进行确定。通过求解SiMOS管和6H-SiC MOS管零温度系数点来稳定偏置电路。结果利用Hspice进行仿真,当温度从300K变化到600K时,SiC运放的增益和相位裕度的变化率分别为2.5%和3.3%,而Si电路的增益从300K的64dB降到600K的-80dB。由于SiC MOS器件沟道迁移率低导致器件的跨导低于相同尺寸下的Si器件,所以其开环增益也小于相同结构和尺寸的Si opamp。结论此电路可以在高温下稳定工作,但是单管的性能较Si单管差。

关键词： 6H-SiC CMOS opamp 零温度系数泄漏电流匹配温度稳定性

A 12 bit 100 MS/s pipelined analog to digital converter without calibration

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Journal of Semiconductors 2010年第11期31卷 100-104页

作者：蔡小波李福乐张春王志华 Institute of Microelectronics Tsinghua University

A 1.8 V 12 bit 100 MS/s pipelined analog to digital converter（ADC） in a 0.18μm complementary metal-oxide semiconductor process is *** first stage adopts a 3.5 bit structure to relax the capacitor matching requirements.A bootstrapped switch and a scaling down technique are used to improve the ADC＇s linearity and save power dissipation,*** a 15.5 MHz input signal,the ADC achieves 79.8 dB spurious-free dynamic range and 10.5 bit effective number of bits at 100 MS/*** power consumption is 112 mW at a 1.8 V supply,including output *** chip area is 3.51 mm2,including pads.

关键词： pipelined ADC multi-bit opamp low power

基于恒流二极管(CRD)的运算放大器低功耗研究

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电子设计工程 2015年第15期23卷 13-15页

作者：邹序武丁召杨发顺刘娇贵州大学大数据与电子信息学院贵州贵阳550025

基于CRD对741双极型通用集成运放进行改进研究,通过CRD替代双极型集成运算放大器(opamp)输入级及偏置电路中做为恒流源的双极型器件,并利用Multisim 10和Cadence进行设计与仿真。结果表明,当电源电压改变时,双极型运算放大器输入级电流... 详细信息

基于CRD对741双极型通用集成运放进行改进研究,通过CRD替代双极型集成运算放大器(opamp)输入级及偏置电路中做为恒流源的双极型器件,并利用Multisim 10和Cadence进行设计与仿真。结果表明,当电源电压改变时,双极型运算放大器输入级电流在0.290 m A到0.433 m A变化,而基于CRD的差分输入级电流恒定在0.239 m A到0.244 m A之间,且电流变化只有0.005 m A。当电源电压恒定在13 V时,双极型运算放大器偏置电流达到0.739 m A,而基于CRD偏置电路电流只有0.222 m。由此可知,基于CRD的运算放大器能实现更低功耗。

关键词： CRD 恒流源 opamp 低功耗

New Integrators and Differentiators Using a MMCC

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Circuits and Systems 2012年第3期3卷 288-294页

作者： Palaniandavar Venkateswaran Rabindranath Nandi Sagarika Das B. P. Poddar Institute of Management & Technology Kolkata-700052 India Department of Electronics & Telecommunication Engineering Jadavpur University Kolkata-700032 India

Using the new building block Multiplication-Mode Current Conveyor (MMCC), some inverting/non-inverting type integrator and differentiator designs are presented, wherein the time constant (τ) is tuned electronically. The MMCC is implemented by a readily available chip-level configuration using a multiplier (ICL 8013) and a current feedback amplifier (AD-844 IC) CFA. Detailed analysis, taking into account the device non-idealities, had been carried out that indicates slight deviations affecting the values of the nominal time constant but the design is practically insensitive to the port mismatch errors (ε). Satisfactory response on wave conversion, for signal frequencies up to 600 Khz had been verified with both hardware circuit test and PSPICE macromodel simulation.

关键词： Voltage-Controlled Oscillator Multiplication Mode Current Conveyor (MMCC) Current Feedback opamp (CFA) Quadrature Oscillator