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A 1G-cell floating-gate nor flash memory in 65 nm technology with 100 ns random access time

Science China(Information Sciences) 2015年第4期58卷 158-165页

作者： LIU LiFang WU Dong LIU XueMei HUO ZongLiang LIU Ming PAN LiYang Institute of Microelectronics University of Tsinghua Tsinghua National Laboratory for Information Science and Technology Laboratory of Nano-Fabrication and Novel Devices Integrated Technology Institute of MicroelectronicsChinese Academy of Sciences

A 1G-cell nor flash memory chip has been designed and fabricated successfully with 65 nm technology. To compromise the array efficiency and chip speed, the paper establishes an array model including parasitics of the whole array, and optimizes the sector structure as 512 wordlines(WLs) and 4096 bitlines(BLs).Furthermore, by adding other models of long and thin metal lines, we have analyzed the speed of critical circuit nodes. As a result, the agreement of WL delay between simulation and measurement verifies the accuracy of the array model and lines models. The test results indicate that the chip achieves random access time of 100 ns and page read time of 25 ns under 3.3 V voltage supply.

关键词： nor flash memory giga-level 65 nm technology array efficiency high speed

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Random telegraph noise on the threshold voltage of multi-level flash memory

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Chinese Physics B 2017年第1期26卷 547-551页

作者： Yiming Liao Xiaoli Ji Yue Xu Chengxu Zhang Qiang Guo Feng Yan College of Electronic Science and Engineering Nanjing University Nanjing 210093 China Quality and Reliability Engineering Wuhan Xinxin Semiconductor Manufacturing Company Wuhan China College of Electronic Science and Engineering Nanjing University of Posts and Telecommunications Nanjing 210003 China

We investigate the impact of random telegraph noise（RTN） on the threshold voltage of multi-level nor flash *** is found that the threshold voltage variation（？Vth） and the distribution due to RTN increase with the programmed level（Vth） of flash cells. The gate voltage dependence of RTN amplitude and the variability of RTN time constants suggest that the large RTN amplitude and distribution at the high program level is attributed to the charge trapping in the tunneling oxide layer induced by the high programming voltages. A three-dimensional TCAD simulation based on a percolation path model further reveals the contribution of those trapped charges to the threshold voltage variation and distribution in flash memory.

关键词： random telegraph noise nor flash memory percolation path oxide charges

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Optimized operation scheme of flash-memory-based neural network online training with ultra-high endurance

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Journal of Semiconductors 2024年第1期45卷 33-37页

作者： Yang Feng Zhaohui Sun Yueran Qi Xuepeng Zhan Junyu Zhang Jing Liu Masaharu Kobayashi Jixuan Wu Jiezhi Chen School of Information Science and Engineering(ISE) Shandong UniversityQingdao 266200China Neumem Co. LtdHefei 230093China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics of Chinese Academy of SciencesBeijing 100084China Institute of Industrial Science The University of TokyoTokyoJapan

With the rapid development of machine learning,the demand for high-efficient computing becomes more and more *** break the bottleneck of the traditional Von Neumann architecture,computing-in-memory(CIM)has attracted increasing attention in recent *** this work,to provide a feasible CIM solution for the large-scale neural networks(NN)requiring continuous weight updating in online training,a flash-based computing-in-memory with high endurance(10^(9) cycles)and ultrafast programming speed is *** the one hand,the proposed programming scheme of channel hot electron injection(CHEI)and hot hole injection(HHI)demonstrate high linearity,symmetric potentiation,and a depression process,which help to improve the training speed and *** the other hand,the low-damage programming scheme and memory window(MW)optimizations can suppress cell degradation effectively with improved computing *** after 109 cycles,the leakage current(I_(off))of cells remains sub-10pA,ensuring the large-scale computing ability of *** characterizations are done on read disturb to demonstrate its robust *** processing CIFAR-10 tasks,it is evident that~90%accuracy can be achieved after 109 cycles in both ResNet50 and VGG16 *** results suggest that flash-based CIM has great potential to overcome the limitations of traditional Von Neumann architectures and enable high-performance NN online training,which pave the way for further development of artificial intelligence(AI)accelerators.

关键词： nor flash memory computing-in-memory endurance neural network online training

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flash-based in-memory computing for stochastic computing in image edge detection

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Journal of Semiconductors 2023年第5期44卷 145-149页

作者： Zhaohui Sun Yang Feng Peng Guo Zheng Dong Junyu Zhang Jing Liu Xuepeng Zhan Jixuan Wu Jiezhi Chen School of Information Science and Engineering(ISE) Shandong UniversityQingdao 266000China Shandong Sinochip Semiconductors Co.Ltd Jinan 250101China Neumem Co. LtdHefei 230088China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics of Chinese Academy of SciencesBeijing 100029China

The“memory wall”of traditional von Neumann computing systems severely restricts the efficiency of data-intensive task execution,while in-memory computing(IMC)architecture is a promising approach to breaking the *** variations and instability in ultra-scaled memory cells seriously degrade the calculation accuracy in IMC architectures,stochastic computing(SC)can compensate for these shortcomings due to its low sensitivity to cell ***,massive parallel computing can be processed to improve the speed and efficiency of the *** this paper,by designing logic functions in nor flash arrays,SC in IMC for the image edge detection is realized,demonstrating ultra-low computational complexity and power consumption(25.5 fJ/pixel at 2-bit sequence length).More impressively,the noise immunity is 6 times higher than that of the traditional binary method,showing good tolerances to cell variation and reliability degradation when implementing massive parallel computation in the array.

关键词： in-memory computing stochastic computing nor flash memory image edge detection

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