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2005 6th International Conference on ASIC

作者： Hao Li Srinivas Katkoori Zhipeng Liu Department of Computer Science and Engineering University of North Texas Denton TX 76203USA Department of Computer Science and Engineering University of South Florida Tampa FL 33620 USA Department of Computer Science and Technology Tsinghua University

＜正＞We propose a high level synthesis design flow in order to improvement the circuit performance once the placement phase is *** use a high level synthesis system known as Automatic Design Instantiation（AUDI） to generate a registertransfer level（RTL） *** netlist is then given to a Xilinx CAD tool for physical *** of routing the design right after the placement phase,we make use of the estimated interconnect delay,generate a guidance and give it to the high level synthesis *** guidance consists of estimated timing information as well as instructions for producing a new netlist to improve the circuit *** design is finally routed on a satisfying *** performance-driven high level synthesis framework yields significantly better results as compared with designs generated by a plain top-down design flow.

关键词： Feedback high level synthesis Circuit optimization Delay estimation Design automation Circuit synthesis Routing Phase estimation Integrated circuit interconnections Timing

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Technical Decisions on Several Key Problems in VHDLhigh level synthesis System

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Journal of Computer Science & Technology 1999年第6期14卷 565-571页

作者：刘明业张东晓许庆平 ASICResearchCenter BeijingInstituteofTechnologyBeijing100081PR.China

This paper studies the realization of the high level synthesis fromsystem behavioral (algorithmic or functional) description of circuits to structuraldescription of RTL and logic level. Based on Xilinx-FPGA libraryl the structural description is mapped to technology-dependent ASIC, and FPGA chips are *** main points in this paper include the technical decision of each subsystem in aVHDL high level synthesis system HLS/BIT. The system is realized on SUN SPARC2, and correct running results are given.

关键词： high level synthesis VHDL data flow control flow technologyMapping

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维普期刊数据库

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A SCHEDULING SCHEME WITH DYNAMIC FREQUENCY CLOCKING AND MULTIPLE VOLTAGES FOR LOW POWER DESIGNS

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Journal of Electronics(China) 2007年第4期24卷 572-576页

作者： Wen Dongxin Wang Ling Yang Xiaozong Department of Computer Science an-d Technology -I-Iarb（n Institute of Technology Harbin 150001 China

In this letter, a scheduling scheme based on Dynamic Frequency Clocking (DFC) and multiple voltages is proposed for low power designs under the timing and the resource constraints. Unlike the conventional methods at high level synthesis where only voltages of nodes were considered, the scheme based on a gain function considers both voltage and frequency simultaneously to reduce energy consumption. Experiments with a number of DSP benchmarks show that the proposed scheme achieves an effective energy reduction.

关键词： Scheduling scheme Dynamic Frequency Clocking (DFC) Multiple voltages high level synthesis

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维普期刊数据库

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Simultaneous Partitioning and Scheduling Algorithm for Clustered Architecture

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Journal of Semiconductors 2004年第4期25卷 383-387页

作者：王磊魏少军清华大学微电子学研究所北京100084

Clustered architecture is selected for high level synthesis,and a simultaneous partitioning and scheduling algorithm are *** with traditional methods,circuit performance can be *** show the efficiency of the method.

关键词： high level synthesis scheduling partitioning clustered architecture

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