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Implementation of AVS Jizhun decoder with hw/sw partitioning on a coarse-grained reconfigurable multimedia system

Science China(Information Sciences) 2014年第8期57卷 166-179页

作者： LIU LeiBo CHEN YingJie YIN ShouYi ZHOU Li YUAN Hang WEI ShaoJun Institute of Microelectronics Tsinghua University Institute of Microelectronics of Chinese Academy of Sciences

In this paper,a TPP(Task-based Parallelization and Pipelining)scheme is proposed to implement AVS(Audio Video coding Standard)video decoding algorithm on REMUS(REconfigurable MUltimedia System),which is a coarse-grained reconfigurable multimedia *** AVS decoder has been implemented with the consideration of hw/sw optimized *** parallel techniques,such as MB(Macro-Block)-based parallel and block-based parallel techniques,and several pipeline techniques,such as MB level pipeline and block level pipeline techniques are adopted by hardware implementation,for performance improvement of the AVS ***,most computation-intensive tasks in AVS video standards,such as MC(Motion Compensation),IP(Intra Prediction),IDCT(Inverse Discrete Cosine Transform),REC(REConstruct)and DF(Deblocking Filter),are performed in the two RPUs(Reconfigurable Processing Units),which are the major computing engines of *** to the proposed scheme,the decoder introduced here can support AVS JP(Jizhun Profile)1920×1088@39fps streams when exploiting a 200 MHz working frequency.

关键词： AVS video decoder coarse-grained reconfigurable multimedia system computation-intensive tasks parallelization and pipelining hw/sw partitioning

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Implementation of multi-standard video decoder on a heterogeneous coarse-grained reconfigurable processor

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Science China(Information Sciences) 2014年第8期57卷 216-229页

作者： LIU LeiBo CHEN YingJie WANG Dong YIN ShouYi WANG Xing WANG Long LEI Hao CAO Peng WEI ShaoJun Institute of Microelectronics Tsinghua University

This paper proposes a task-based hybrid parallel and hybrid pipeline(THPHP)scheme to implement multi-standard video algorithms,including MPEG-2,H.264,and audio video coding standard(AVS),on a heterogeneous coarse-grained reconfigurable processor,called the reconfigurable multimedia system(REMUS).The proposed schemes greatly improve decoding performance and satisfy the real-time requirements of various high-definition(HD)video decoding *** THPHP,we propose both a task-based hybrid parallel scheme,in which macro-block(MB)-level,block-level,and sub-block-level decoding tasks are parallelized to improve data processing throughput,and a hybrid pipeline scheme,in which slice-level,MB-level,block-level and sub-block-level computations are pipelined to improve ***-intensive tasks,such as motion compensation,intra prediction,inverse discrete cosine transform,reconstruction,and deblocking filter,are implemented on two reconfigurable processing units,which are the core computing engines of *** to the proposed schemes,the implementations can achieve H.264 high profile(HP)1920×1080@30 fps streams,AVS Jizhun profile(JP)1920×1080@39 fps streams,and MPEG-2 main profile(MP)1920×1080@41 fps streams when working at 200 MHz *** with XPP-III(a commercial reconfigurable processor),when implementing H.264 HD decoding,the performance and energy efficiency on REMUS are improved by1.81×and 14.3×,respectively.

关键词： multi-standard video decoder coarse-grained reconfigurable multimedia system computationintensive tasks parallelization and pipelining hw/sw partitioning

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Graph Reduction Algorithm for Hardware/Software partitioning

Graph Reduction Algorithm for Hardware/Software Partitioning

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2011 International Conference on Control, Automation and Systems Engineering(CASE)

作者： Hui Li Wenju Liu Honglei Han Computer Science and Software Institution Tianjin Polytechnic University

One of the most crucial steps in the design of embedded systems is Hardware/Software(hw/sw) partitioning, that is, deciding which components of the system should be implemented in hardware and which ones in software. Most formulations of the hw/sw partitioning problem are NP-hard, so most of the research efforts on hw/sw partitioning has focused on developing efficient heuristic. In this paper, we did not committed to finding effective methods of hw/sw partitioning, but focusing on the pre-process for the task graph before the hw/sw partitioning, and to find all the sub-graphs which meet the requirements. Simplification of the original task graph, so that the partitioning will be more accurately and faster, and it also can save the hardware area effectively.

关键词： hw/sw partitioning task graph pre-process sub-graph

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Graph Reduction Algorithm for Hardware/Software partitioning

Graph Reduction Algorithm for Hardware/Software Partitioning

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2011 2nd Asia-Pacific Conference on Wearable Computing Systems (APWCS 2011);2011 International Conference on Intelligent Control and Information Technology(ICICIT 2011)

作者： Hui Li Wenju Liu Honglei Han Computer Science and Software Institution Tianjin Polytechnic University

One of the most crucial steps in the design of embedded systems is Hardware/Software（hw/sw） partitioning,that is,deciding which components of the system should be implemented in hardware and which ones in *** formulations of the hw/sw partitioning problem are NP-hard,so most of the research efforts on hw/sw partitioning has focused on developing efficient *** this paper,we did not committed to finding effective methods of hw/sw partitioning,but focusing on the pre-process for the task graph before the hw/sw partitioning,and to find all the sub-graphs which meet the *** of the original task graph,so that the partitioning will be more accurately and faster,and it also can save the hardware area effectively.

关键词： hw/sw partitioning task graph pre-process sub-graph

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