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EVOLUTION OF MICROSTRUCTURE OF Sn-Ag-Cu LEAD-FREE flip chip SOLDER JOINTS DURING AGING PROCESS

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Acta Metallurgica Sinica(English Letters) 2006年第4期19卷 301-306页

作者： Y.H. Tian C.Q. Wang W.F. Zhou State Key Lab of Advanced Welding Production and Technology Harbin Institute of Technology Harbin 150001 China

flip chip bonding has become a primary technology that has found application in the chip interconnection process in the electronic manufacturing industry in recent years. The solder joints of the flip chip bonding are small and consist of complicated microstructures such as Sn solution, eutectic mixture, and intermetallic compounds （IMCs）, whose mechanical performance is quite different from the original solder bulk. The evolution of microstructure of the flip chip solder joints under thermal aging was analyzed. The results show that with an increase in aging time, coarsening of solder bulk matrix and AuSn4 IMCs occurred within the solder. The IMCs that are formed at the bottom side of the flip chip bond were different from those on the top side during the aging process. （Cu, Ni, Au）0Sn5 were formed at the interfaces of both sides, and large complicated （Au,Ni, Cu）Sn4 IMCs appeared for some time near the bottom interface after aging, but they disappeared again and thus （Cu,Ni, Au ）0Sn5 IMC thickness increased considerably. The influence of reflow times during the flip chip bonding （as-bonded condition） on the characteristics of interfacial IMCs was weakened when subjected to the aging process.

关键词： lead free solder flip chip aging

flip chip封装零件组装良率提升方法的研究

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Flip Chip封装零件组装良率提升方法的研究

作者：罗建辉上海交通大学

学位级别：硕士

随着移动通信产品往轻薄短小的方向发展,产品制程比以往更复杂,产品良率的提升更为艰难,特别当集成电路封装形式由BGA(Ball Grid Array)过渡到flip chip时,往往都会遭遇一些良率问题。本文对封装的发展、flip chip封装、需求及应用等进... 详细信息

随着移动通信产品往轻薄短小的方向发展,产品制程比以往更复杂,产品良率的提升更为艰难,特别当集成电路封装形式由BGA(Ball Grid Array)过渡到flip chip时,往往都会遭遇一些良率问题。本文对封装的发展、flip chip封装、需求及应用等进行了介绍。对其组装流程、失效分析流程、以及实际应用过程中遭遇到的良率问题通过DOE(Design of Experiment)验证等方法进行了重点研究:(1)对flip chip来料进行外观检验,特别对焊接凸块的外观进行规范。每批次入料抽取32片进行外观确认,排除来料不良;(2)改变flip chip区域的PCB的设计。将焊盘间距小于0.45mm的NSMD(Non-Solder Mask Design)PCB焊盘设计改成SMD(Solder Mask Design),并将高度Z限制为6μmflip chip顶部UBM宽度的1.1～1.2倍,可降低填胶缺失率约13.5%;(3)改变PCB焊盘(PAD)的表面处理。表面处理药水由NPR4变成同等条件下抗氧化能力更强的NPR8,以减少出现“黑垫”的问题。可降低拒焊缺失率约3%;(4)PCB投放至回焊炉前,将PCB置于流量大于80lpm的氮气中,进行125℃持续4小时的烘烤。使基板与flip chip之间的匹配CTE(Coefficient of Thermal Expansion)差异减小,从而降低由内应力引发焊接失效1.81%。当将这些改善方法以组合的方式一起导入,缺失率可降低至0.145%左右,最终良率可获得18.165%的提升。以防问题在新项目上重现,这些方法导入各工程的CTF(Critical to Function)检查表中并形成工程树,然后映射到DFX(Design for Manufacture,Test,Service…)验证库及设计库。

关键词： flip chip 缺失率外观检验 SMD 表面处理

Preparation and atmospheric wet-reflow of indium microbump for low-temperature flip-chip applications

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Advances in Manufacturing 2023年第2期11卷 203-211页

作者： Wen-Hui Zhu Xiao-Yu Xiao Zhuo Chen Gui Chen Ya-Mei Yan Lian-Cheng Wang Gang-Long Li State Key Laboratory of High Performance Complex Manufacturing Central South UniversityChangsha410083People's Republic of China College of Mechanical and Electrical Engineering Central South UniversityChangsha410083People's Republic of China School of Mechanical and Electrical Engineering East China University of TechnologyNanchang330013People's Republic of China

An urgent demand for lowering bonding temperature has been put forward by advanced flip-chip integration such as micro-LED packaging and heterogeneous integration of semiconductor *** microbump with low-melting point has attracted attention for its potential use as the interconnection intermediate,and the development of its fabrication process is therefore of great *** reveal the critical process factors for successfully fabricating a high-density In microbump array,this paper investigated a simple process flow of In patterning and reflow and detailed the flux-assisted wet reflow *** process conditions,including the patterned In volume,alignment accuracy,reflow reagent liquidity,and temperature profile,were described,with a particular emphasis on the role of surface tension of molten indium film during the formation of spherical microbumps.A high-density indium ball array with an overall yield greater than 99.7%can be obtained,which suggests that the In patterning and wet-reflow processes are robust and that a high-quality microbump array could be readily formed with low equipment ***,the interfacial reaction characteristics between In microbump and Au adhesion layer were investigated under thermal aging conditions,which revealed lateral intermetallic growth of AuIn2 compound and well-retained interfacial strength even after prolonged aging.

关键词： flip chip Reflow Indium microbump Au-In intermetallics

Light-extraction enhancement of freestanding GaN-based flip-chip light-emitting diodes using two-step roughening methods

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Journal of Semiconductors 2013年第11期34卷 49-52页

作者：安铁雷孙波魏同波赵丽霞段瑞飞廖元勋李晋闽伊福廷 Institute of Semiconductors Chinese Academy of Sciences Institute of High Energy Physics Chinese Academy of Sciences

The light extraction enhancement of freestanding GaN-based flip-chip light-emitting diodes （FS- FCLEDs） using two-step roughening methods is investigated. The output power of LEDs fabricated by using one-step and two-step roughening methods are compared. The results indicate that two-step roughening meth- ods show more potential for light extraction. Compared with flat FS-FCLEDs, the output power of FS-FCLEDs with a nanotextured hemisphere surface shows an enhancement of 90.7%.

关键词： freestanding GaN flip chip LED CsCI wet etching light extraction

Preparation of GaN-on-Si based thin-film flip-chip LEDs

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Journal of Semiconductors 2013年第5期34卷 35-37页

作者：章少华封波孙钱赵汉民 School of Materials Science and Technology Nanchang University Lattice Power(Jiangxi) Corporation

GaN based MQW epitaxial layers were grown on Si （111） substrate by MOCVD using AIN as the buffer layer. High light extraction LEDs were prepared by substrate transferring technology in combination with thin-film and flip-chip design. The blue and white 1.1 × 1.1 mm2 LED lamps are measured. The optical powers and external quantum efficiency for silicone encapsulated blue lamp are 546 mW, and 50.3% at forward current of 350 mA, while the photometric light output for a white lamp packaged with standard YAG phosphor is 120.1 lm.

关键词： silicon substrate GaN flip chip LED

基于机器视觉的flip chip芯片检测与定位算法研究

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基于机器视觉的FLIP CHIP芯片检测与定位算法研究

作者：李茹哈尔滨工业大学

学位级别：硕士

随着贴片机和电子封装技术的发展,flip chip芯片成为表面贴装元件中的热点,而在贴片机的工作流程中,对芯片的缺陷检测和位姿获取是保证芯片能够正确贴装的关键。本文针对贴片机视觉系统中flip chip芯片的检测与定位系统展开深入研究,在... 详细信息

随着贴片机和电子封装技术的发展,flip chip芯片成为表面贴装元件中的热点,而在贴片机的工作流程中,对芯片的缺陷检测和位姿获取是保证芯片能够正确贴装的关键。本文针对贴片机视觉系统中flip chip芯片的检测与定位系统展开深入研究,在分析了flip chip芯片的封装特点和国内外研究现状后,设计了包括芯片图像预处理、芯片图像特征提取和芯片缺陷检测与位姿获取的flip chip检测与定位算法流程,具体研究内容如下:对flip chip芯片采集过程中可能出现的噪声、光照不均匀和焊锡高亮度干扰点进行图像预处理,得到一幅理想的二值图像。首先采用基于概率统计的光照不均匀校正算法对噪声环境下芯片原图像中的光照不均匀现象进行校正,再选用最大类间方差法将芯片图像中的目标区域与背景区分开,最后采用形态学操作中的开操作和闭操作去除Otsu二值化后出现的白色和黑色干扰区域。将二值图像进行连通区域标记进而获取目标轮廓,再以轮廓的Hu不变矩为判定依据将flip chip芯片的焊球轮廓筛选出来,剔除目标轮廓中的干扰轮廓。对比分析基于灰度相似性的区域生长法和基于灰度不连续性的Canny边缘检测法后,采用基于灰度不连续性的特征提取方法,将芯片焊球的轮廓图像与Canny边缘检测图像进行与操作,对边缘点进行距离滤波后获得高精度的焊球边缘点集。采用最小二乘圆拟合的方法简单精确表示芯片中焊球的位置,根据拟合圆的参数获取焊球个数、焊球直径、焊球位置等芯片重要数据信息。将检测到的芯片数据信息与标准数据信息相对比,返回待检测芯片的错误码及缺陷类型。在确保芯片完好无损后,采用基于参数空间的点模匹配算法实现对芯片的定位,该算法不需要绘制模板图像,不完全依赖于外围焊球中心坐标,同时针对不对称或不规则的焊球分布类型芯片也可以实现准确的定位。最后对完整的检测与定位算法进行鲁棒性与通用性测试,通过对测试结果的分析可以看出本文所提出的算法可以满足贴片机精度及速度要求,可以检测各种类型焊球分布的flip chip芯片。

关键词： flip chip 图像预处理特征提取缺陷检测位姿获取

flip chip Die-to-Wafer Bonding Review:Gaps to High Volume Manufacturing

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Semiconductor Science and Information Devices 2022年第1期4卷 8-13页

作者： Mario Di Cino Feng Li Department of Electrical and Computer Engineering University of IdahoMoscowIdaho83844USA

flip chip die-to-wafer bonding faces challenges for industry adoption due to a variety of technical gaps or process integration factors that are not fully developed to high volume manufacturing(HVM)*** this paper,flip-chip and wire bonding are compared,then flip-chip bonding techniques are compared to examine advantages for scaling and *** recent 3-year trends in flip-chip die-to-wafer bonding are reviewed to address the key gaps and challenges to HVM ***,some thoughts on the care needed by the packaging technology for successful HVM introduction are reviewed.

关键词： flip chip Die-to-Wafer(D2W) chip-to-Wafer(C2W) chip-scale packaging(CSP) High volume manufacturing(HVM) Known good die(KGD) Through silicon via(TSV) Reliability

Flux/underfill Compatibility Study for flip-chip Assembly Process

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Flux/underfill Compatibility Study for Flip-chip Assembly Pr...

flip chip结构的IC信号完整性仿真分析

International Conference on Information and Electronics Engineering（ICIEE 2011）

作者： Phuthanate Phoosekieaw Sanya Khunkhao Faculty of Engineering Department of Electrical Engineering Sripatum University61 Phaholyothin RdJatujakBangkok 10900

The rapid uptake of flip-chip technology within the electronics industry due to their better thermal performance,smaller size,lower profile,light weight,and higher input/output density,the solder joints together with underfill in flip chip package serve as a mechanical mechanism for resisting the thermal deformation induced by the coefficient of thermal expansion（CTE） mismatch between silicon die and *** materials are employed in flip-chip assemblies to enhance solder joint reliability *** adhesion of underfills with solders is important to the integrity of the flip-chip *** effect of temperature and humidity aging as well as flux residue on adhesion strength was also investigated.

关键词： flip chip Underfill Tacky flux

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单片机与嵌入式系统应用 2023年第10期23卷 12-15页

作者：李少聪杨录吕俊文闫慧欣中北大学信息与通信工程学院太原030051

针对flip chip封装型芯片设计过程中存在的传输线阻抗不连续与串扰过大等问题,从层叠设置与板材介质厚度两个角度提出了一种基于阻抗、串扰的仿真分析设计方法,主要涉及两个方面:对于由信号参考平面被分割而造成的阻抗突变问题,通过添... 详细信息

针对flip chip封装型芯片设计过程中存在的传输线阻抗不连续与串扰过大等问题,从层叠设置与板材介质厚度两个角度提出了一种基于阻抗、串扰的仿真分析设计方法,主要涉及两个方面:对于由信号参考平面被分割而造成的阻抗突变问题,通过添加参考平面而使信号具有完整的回流路径,使得传输线的阻抗在平面分割处由167.5Ω降至52.5Ω;对于因布线密度过大而造成的走线之间的串扰系数偏高的问题,通过减小板材的介质厚度使传输线间串扰系数的最大值从17.26%降至14.01%。仿真结果表明,此设计方法有效降低了芯片设计中潜在的信号完整性风险,提高了芯片的可靠性和稳定性。

关键词： flip chip IC 信号完整性阻抗串扰

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