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Pulse control of frequency and width for a real-time independently adjustable laser source

Frontiers of Information Technology & electronic Engineering 2021年第10期22卷 1379-1389页

作者： Zhiwei YANG Xu WU Deqin OUYANG Encheng ZHANG Huibin SUN Shuangchen RUAN Guangdong Provincial Key Laboratory of Micro/Nano Optomechatronics Engineering College of Physics Science and Optoelectronic EngineeringShenzhen UniversityShenzhen 518060China College of Sino-German Intelligent Manufacturing Shenzhen Technology UniversityShenzhen 518118China

A set of semiconductor laser pulse seed sources based on an embedded chip is *** greatest feature is that the optical pulse frequency and width can be independently adjusted in real *** pulse seed sources can be switched independently and online from the gain-switched mode to the quasi-continuous wave mode to obtain optimal optical parameters for specific *** explore the physical mechanism of the semiconductor laser source,the rate equation that describes the carrier-photon transient change in a semiconductor laser cavity is numerically derived and ***,problems that need to be considered while designing the drive circuit are *** system evaluation indicates that the optical pulse frequency adjustment range is 250 Hz to 42 MHz,and the narrowest optical pulse output width is 80 *** pulse seed source can drive semiconductor lasers with different central wavelengths(1064,1550,and 1970 nm),and can also simultaneously drive two semiconductor lasers and output dual-band optical *** can be used as a seed source for general high-power optical systems,and exhibits good application value and extensive market prospects.

关键词： Electric variable control electronic design automation and methodology Optical pulse generation Optical control

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A Technique to Exploit Memory Locality for Fast Instruction Set Simulation

A Technique to Exploit Memory Locality for Fast Instruction ...

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2005 6th International Conference on ASIC

作者： Wei Qin Bo Hu Boston University Fudan University

＜正＞To verify software and system functionality during the design process of complex SoCs,designers routinely use instruction set simulators（ISSs） as high level processor ***,an ISS needs to simulate billions of target instructions to verify a single task of the system in design,which is a very time-consuming process. Therefore,the simulation speed of ISSs has become one important concern of SoC *** this paper,we present a new techmque to improve the speed of ***, we focus on the translation of memory addresses between the target memory space and the host memory *** translation is performed by a hash table in many ISS *** accelerate the translation,we introduce a software cache called translation buffer（TB） to cache the hashing results for quick future *** properly chosen TB sizes,our implementation effectively exploits the abundant locality inherent in the memory footprints of real-world application programs and greatly reduces the overall address translation *** integrated the technique into three popular ISSs and achieved a 15-32% improvement in simulation speed.

关键词： Computational modeling Application software Acceleration Program processors Hardware electronic design automation and methodology Registers Read-write memory Software systems Process design

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