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Adding Pseudo-Random Test Sequence Generator in the Test Simulator for DFT Approach

Computer Technology and Application 2012年第7期3卷 463-470页

作者： Afaq Ahmad Dawood Al-Abri Sayyid Samir AI-Busaidi Department of Electrical and Computer Engineering College of Engineering Sultan Qaboos University Muscat 123 Sultanate of Oman

This paper presents modified version of a realistic test tool suitable to Design For Testability （DFT） and Built-ln Self Test （BIST） environments. A comprehensive tool is developed in the form of a test simulator. The simulator is capable of providing a required goal of test for the Circuit Under Test （CUT）. The simulator uses the approach of fault diagnostics with fault grading procedures to provide the optimum tests. The current version of the simulator embeds features of exhaustive and pseudo-random test generation schemes along with the search solutions of cost effective test goals. The simulator provides facilities of realizing all possible pseudo-random sequence generators with all possible combinations of seeds. The tool is developed on a common Personal Computer （PC） platform and hence no special software is required. Thereby, it is a low cost tool hence economical. The tool is very much suitable for determining realistic test sequences for a targeted goal of testing for any CUT. The developed tool incorporates flexible Graphical User Interface （GUI） procedures and can be operated without any special programming skill. The tool is debugged and tested with the results of many bench mark circuits. Further, this developed tool can be utilized for educational purposes for many courses such as fault-tolerant computing, fault diagnosis, digital electronics, and safe-reliable-testable digital logic designs.

关键词： digital system testing built-in self test design for testability test vector pseudo-random test sequence linear feedbackshift registers fault diagnosis fault collapsing realistic test fault cover iteration.

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