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Patterning Defect Study for Process Integration Engineering Using Pattern Fidelity Monitoring with Review SEM Images

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Journal of Microelectronic Manufacturing 2019年第2期2卷 21-25页

作者： Yu Zhang Abhishek Vikram Ming Tian Tianpeng Guan Jianghua Leng Baojun Zhao Lei Yan Wei Hu Guojie Chen Hui Wang Gary Zhang Wenkui Liao Shanghai Huali Microelectronics Corp. Pudong District Shanghai China 201203 Anchor Semiconductor Shanghai China 200001 Anchor Semiconductor Santa Clara CA USA 95051

Normally the optical wafer inspection tools are used for advanced process control in high volume manufacturing of semiconductor devices. The SEM Review is done for limited sample of inspection defects to do defect based process characterization. The defect classes that are monitored normally indicate process and random defect issues. There is limited to no information of patterning related issues in real time defect monitor. Moreover, with the objective of process integration engineering of multiple processes it becomes harder to see the evolution of a defect in the line. The die-to-database Pattern Monitor (D2DB-PM) solution has addressed this problem. It uses the existing high resolution images from the Review and Metrology tools and compares the pattern shapes with the design reference. This way it captures patterning deviations in real time. Here we report the subtle defect problem encountered in process integration and the results from using the D2DB-PM solution. We found that this approach reduces the workload on CDSEM tools by analyzing SEM Review images instead and the automated reports improves the efficiency of all process teams.

关键词： die-to-database Pattern Monitor After Develop Inspection (ADI) After Etch Inspection (AEI) SEM Review CDSEM pattern centric pattern monitor

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Pattern-Centric Computational System for Logic and Memory Manufacturing and Process Technology Development

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Journal of Microelectronic Manufacturing 2020年第4期3卷 82-94页

作者： Chenmin Hu Khurram Zafar Abhishek Vikram Geoffrey Ying Anchor Semiconductor Santa ClaraUSA95051

Chip designers employ computer-aided design,circuit simulation,and design rule check *** engineers employ model-based OPC(Optical Proximity Correction)and model-based print-simulation *** inspection teams employ Aerial Image Measurement Systems®and Virtual Stepper®*** teams are accustomed to evaluating and deploying state-of-the-art computational *** real-silicon fabrication begins,however,the teams responsible for line monitoring,wafer inspection,and yield attainment operate without the benefit of similarly advanced computational *** this paper we describe such a system and explore its applications and *** system has received three ***[1-3]and brings together the significant potential of CAD(Computer Aided Design)layout(GDS,OASIS),die-to-database,and Machine Learning to build a dynamic,self-improving computational *** care area generation,advanced machine learning-based SEM(Scanning Electron Microscope)sampling that optimizes both DOI(Defect of Interest)capture rate and discovery of new defect types,comprehensive extraction of all Information of Interest(IOI)from all SEM images,detection of defect types not possible before,massive pattern fidelity analysis,full chip pattern decomposition and risk scoring via machine learning,innovative PWQ(Process Window Qualification)analysis and process window determination,risk assessment of new tape-outs,large scale in-wafer OPC verification and more,the system delivers a comprehensive pattern centric platform for process technology development and manufacturing.

关键词： die-to-database Full Chip Decomposition Machine Learning Defect Discovery Pattern Fidelity Pattern Risk Scoring OPC Verification Process Window Qualification

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