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Design of a high linearity and high gain accuracy analog baseband circuit for DAB receiver

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Journal of Semiconductors 2015年第2期36卷 124-129页

作者：马力王志功徐建吴毅强王俊椋田密陈建平 Institute of RF-and OE-ICs Southeast University

An analog baseband circuit of high linearity and high gain accuracy for a digital audio broadcasting receiver is implemented in a 0.18-μm RFCMOS process.The circuit comprises a 3rd-order active-RC complex filter（CF） and a programmable gain amplifier（PGA）.An automatic tuning circuit is also designed to tune the CF＇s pass band.Instead of the class-A fully differential operational amplifier（FDOPA） adopted in the conventional CF and PGA design,a class-AB FDOPA is specially employed in this circuit to achieve a higher linearity and gain accuracy for its large current swing capability with lower static current consumption.In the PGA circuit,a novel DC offset cancellation technique based on the MOS resistor is introduced to reduce the settling time significantly.A reformative switching network is proposed,which can eliminate the switch resistor＇s influence on the gain accuracy of the PGA.The measurement result shows the gain range of the circuit is 10-50 dB with a 1-dB step size,and the gain accuracy is less than ±0.3 dB.The OIP3 is 23.3 dBm at the gain of 10 dB.Simulation results show that the settling time is reduced from 100 to 1 ms.The image band rejection is about 40 dB.It only draws 4.5 mA current from a 1.8 V supply voltage.

关键词： complex filter automatic tuning PGA receiver DAB dcoc

维普期刊数据库

Design and analysis of 20 Gb/s inductorless limiting amplifier in 65 nm CMOS technology

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Journal of Semiconductors 2014年第10期35卷 91-97页

作者：何睿许建飞闫娜孙杰边历嵌闵昊 Department of Microelectronic Fudan University Jinan Ruitong Electric Service LTD

A high speed inductorless limiting amplifier （LA） in an optical communication receiver with the work- ing speed up to 20 Gb/s is presented. The LA includes an input matching network, a four-stage 3rd order amplifier core, an output buffer for the test and a DC offset cancellation （dcoc）. It uses the active interleaving feedback technique both to broaden the bandwidth and achieve the flatness response. Based on our careful analysis of the dcoc and stability, an error amplifier is added to the dcoc loop in order to keep the offset voltage reasonable. Fabricated in the 65 nm CMOS technology, the LA only occupies an area of 0.45 × 0.25 mm2 （without PAD）. The measurement results show that the LA achieves a differential voltage gain of 37 dB, and a 3-dB bandwidth of 16.5 GHz. Up to 26.5 GHz, the Sddlm and Sdd22 are less than -16 dB and -9 dB. The chip excluding buffer is supplied by 1.2 V VDD and draws a current of 50 mA.

关键词： inductorless limiting amplifier optical communication interleaving feedback dcoc

维普期刊数据库

A novel compact low-power direct conversion receiver for mobile UHF RFID reader

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Science China(Information Sciences) 2012年第10期55卷 2226-2233页

作者： LIU Shan 1*,WANG Xin'An 1*,SHEN JinPeng 1,WANG Bo 1,YE Tao 2 & HUANG Ru 3 1 Key Laboratory of Integrated Microsystems,Peking University Shenzhen Graduate School,Shenzhen 518055,China 2 Hong Kong R&D Centre for Logistics and Supply Chain Management Enabling Technologies,HongKong,China 3 Institute of Microelectronics,Peking University,Beijing 100871,China Key Laboratory of Integrated Microsystems Peking University Shenzhen Graduate School Shenzhen China Hong Kong R&D Centre for Logistics and Supply Chain Management Enabling Technologies HongKong China Institute of Microelectronics Peking University Beijing China

A novel direct conversion receiver with low cost and low power is implemented in a 0.18 μm 1P6M standard CMOS process for a Mobile UHF RFID reader.A highly linear active mixer with low flicker noise and low noise active load is proposed.An efficient and low cost on-chip DC offset voltage canceling scheme is adopted with a high-input-impedance four-input OPAMP to buffer the output of the DC offset canceller(dcoc) block.The receiver has a measured input 1 dB compression point of 2 dBm and a sensitivity of 72 dBm in the presence of the large leakage signal from the transmitter.Only occupying a silicon area of 2.5 mm 2 and consuming 21 mA from a 1.8 V supply,the receiver makes the mobile UHF RFID reader to communicate with a transponder in a distance of 1 m conveniently.

关键词： direct conversion receiver mobile UHF RFID reader low power dcoc active mixer four-input OPAMP

48dB动态范围、37dBm-ⅡP3的CMOS可变增益放大器设计

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48dB动态范围、37dBm-ⅡP3的CMOS可变增益放大器设计

作者：张祖翔华中科技大学

学位级别：硕士

随着通信技术的快速发展，射频通信系统正朝着高集成度、高性能、低功耗等方向发展。可变增益放大器(Variable Gain Amplifier, VGA)作为接收机中重要的组成部分，也引起了业界内众多学者及研究人员的重视。由于射频信号在大气中传播，... 详细信息

随着通信技术的快速发展，射频通信系统正朝着高集成度、高性能、低功耗等方向发展。可变增益放大器(Variable Gain Amplifier, VGA)作为接收机中重要的组成部分，也引起了业界内众多学者及研究人员的重视。由于射频信号在大气中传播，会遇到诸如衰减、噪声等问题，导致信号质量下降，信号幅度变化范围大，对接收机的解调造成了巨大困扰，可变增益放大器能够根据接收信号的强弱自动调节放大增益，始终将信号放大到适合解调的幅度，最终达到缓解接收机基带解调的压力。本文主要研究对象为可变增益放大器的设计，以无线接收机系统为背景，介绍了可变增益放大器在无线接收机系统中的作用，分析了可变增益放大器的常见结构、工作原理及性能指标。最后在此基础上，设计了一款由6位数字信号控制的可变增益放大器。本文基于TSMC0.18μm工艺，设计了一款具有高增益动态范围、高线性度、低功耗的可变增益放大器，其中细调可变增益放大器采用将伪指数近似函数(pseudo-exponential)和泰勒级数近似函数(Taylor series approximation)综合出的新型指数近似函数，同时该可变增益放大器还集成直流漂移消除模块dcoc以及数字控制模块，最终可以实现输入数字信号得到对应的输出增益。本文最后介绍了版图设计的相关注意规则，并给出了本设计的最终版图。

关键词：无线接收机可变增益放大器运算放大器 dcoc 低功耗高线性度

面向IMT-A应用的可变增益放大器（PGA）设计与实现

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面向IMT-A应用的可变增益放大器（PGA）设计与实现

作者：叶向阳山东大学

学位级别：硕士

在无线通信系统中,传输速率越来越大,调制方式越来越复杂,要求越来越长的持续通讯时间、以及越来越高的系统灵敏度,由此,作为收发机芯片主要模块之一的可变增益放大器,系统对其提出的带宽、线性度、功耗和噪声等性能指标也越来越苛刻;而... 详细信息

在无线通信系统中,传输速率越来越大,调制方式越来越复杂,要求越来越长的持续通讯时间、以及越来越高的系统灵敏度,由此,作为收发机芯片主要模块之一的可变增益放大器,系统对其提出的带宽、线性度、功耗和噪声等性能指标也越来越苛刻;而且,采用深亚微米CMOS技术之后,低电源电压使得可变增益放大器在这些指标的折衷问题上面临着诸多挑战。本文基于Cadence EDA平台,采用TSMC的0.18μm工艺设计并实现了面向IMT-A应用的可编程增益放大器(programmable gain amplifier, PGA);为了应用于零中频架构的接收机中,本文还设计实现了直流失调消除电路(dcoc);为了减小静态功耗,本文在设计了普通源随器测试buffer的基础上,另外又设计了AB类输出buffer,使整体电路(不含测试buffer)最大静态直流为17mA,与源极跟随器相比,该电路在实现相同功能的情况下,静态直流小了7mA,且对有用信号的衰减较小;整体芯片面积(包括所有PAD)为800*700um2。根据测试结果,工作电压1.8V,在负载为差分100Ω阻抗的情况下,整体电路增益动态范围可达63dB,采用二进制控制,增益步长为1dB,步长误差在±0.38dB以内;在测试buffer存在约为6dB衰减的情况下,整体电路的最高增益为55dB,-3dB带宽为92MHz,在低增益模式下IIP3可达17.5dBm,1dB压缩点可达5.7dBm;根据仿真结果,高增益模式下在l 0MHz处输入参考噪声(IRN)约为6nV/Hz1/2。本文设计并实现的宽带、大增益动态范围、高线性度的可编程增益放大器,满足了面向IMT-A应用的设计指标要求,为继续进行IMT-A射频前端芯片其他电路模块研究奠定了良好基础。

关键词： PGA dcoc AB类buffer 二进制增益控制