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DAC对玉米DNA甲基化影响及基因表达量变化的研究

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玉米科学 2022年第1期30卷 39-47,52页

作者：张辰杨丽萍李春雷祁新吉林农业大学农学院长春130118 梨树县植物保护检疫站四平梨树136500 吉林省农业科学院玉米研究所/玉米国家工程实验室(长春) 吉林公主岭136100

以5-氮杂-2脱氧胞苷(DAC)处理相应对照玉米幼苗叶片为材料构建转录组测序文库,采用Illumina测序平台进行测序,对差异表达基因进行GO功能分类和KEGG通路分析。最终筛选到差异基因1072个,其中,上调表达基因为646个,下调表达基因为426个。... 详细信息

以5-氮杂-2脱氧胞苷(DAC)处理相应对照玉米幼苗叶片为材料构建转录组测序文库,采用Illumina测序平台进行测序,对差异表达基因进行GO功能分类和KEGG通路分析。最终筛选到差异基因1072个,其中,上调表达基因为646个,下调表达基因为426个。将差异基因富集的生物过程和信号通路进行GO分析,发现主要集中于细胞部分、细胞过程、代谢途径及催化活性等条目中。KEGG分析发现,差异基因主要集中在过氧化物酶体、半乳糖代谢、苯丙烷生物合成及植物激素信号转导等代谢通路中。结果表明,代谢途径的细胞过程、代谢过程、催化活性、苯丙烷生物合成、过氧化物酶体、半乳糖代谢以及植物激素信号转导可能在玉米生长发育中起主导作用。通过亚硫酸盐测序对筛选的3个差异表达基因进行DNA甲基化水平分析,发现处理组CG、CHG位点甲基化率下降显著,由此表明DNA甲基化影响基因的表达。

关键词：玉米 DAC 差异表达基因甲基化水平

Research on Column FPN and Black Level Calibration in Large Array CMOS Image Sensor

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Chinese Journal of Electronics 2021年第2期30卷 268-274页

作者： GUO Zhongjie YU Ningmei WU Longsheng School of Automation and Information Engineering Xi'an University of Technology Xi'an Microelectronic Technology Institute

A technical investigation, research and implementation is presented to correct column fixed pattern noise and black level in large array Complementary metal oxide semiconductor(CMOS) image sensor. Through making a comparison among reported solution, and give large array CMOS image sensor design and considerations,according to our previous analysis on non-ideal factor and error source of piecewise Digital to analog converter(DAC) in multi-channels, an improving accurate piecewise DAC with adaptive switch technique is developed. The research theory has verified by a high dynamic range and low column Fixed pattern noise(FPN) CMOS image sensor prototype chip, which consisting of 8320×8320 pixel array was designed and fabricated in 55 nm CMOS 1P4M standard process. The chip active area is 48 mm×48 mm with a pixel size of 5.7μm×5.7μm. The measured results achieved a high intrinsic dynamic range of 75 d B, a low FPN and black level of 0.06%, a low photo response non-uniformity of 1.5% respectively, and an excellent raw sample image taken by the prototype sensor.

关键词： Image detectors, convertors, and intensifiers CMOS integrated circuits Image sensors CMOS image sensor Column FPN Readout chain DAC

12-bit 2.6 GS/s RF DAC based on return-to-zero technology

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The Journal of China Universities of Posts and Telecommunications 2019年第4期26卷 36-42页

作者： Li Xiaopeng Wang Zhigong Zhang Yi Zhang Youtao Zhang Mi Institute of RF and OE ICs Southeast UniversityNanjing 210096China Nanjing Guobo Electronics Company Limited Nanjing 210016China Nanjing Electronic Devices Institute Nanjing 210016China National and Local Joint Engineering Laboratory of RF Integration and Micro-assembly Technology Nanjing 210046China College of Microelectronics Nanjing University of Posts and TelecommunicationsNanjing 210046China State Key Laboratory of Millimeter Waves Southeast UniversityNanjing 210096China Science and Technology on Monolithic Intergrated Circuits and Modules Laboratory Nanjing 210016China

A 12-bit 2.6 GS/s radio frequency digital to analog converter(RF DAC)based on 1 um GaAs heterojunction bipolar transistor(HBT)process is presented.The DAC integrates a 4:1 multiplexer to reduce the data rate of input ports,which greatly facilitates the application.DAC core adopts 4+8 segmented current steering structure.R-2R ladder network is used for 8 least significant bit(LSB)to realize binary current weighting and thermometer coding is used for 4 most significant bit(MSB).Return-to-zero(RZ)technology is used to expand the effective bandwidth of DAC output to the third Nyquist band.The proposed DAC has a better output power flatness and spurious-free dynamic range(SFDR).Compared to traditional DAC,measured results demonstrate that the output power of this RZ DAC is increased by 33 dB and the SFDR is enhanced by 27 dB near the second Nyquist band.

关键词： DAC RZ Nyquist band

基于模拟伺服的多轴EtherCAT协议设计

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仪表技术与传感器 2023年第2期 69-72,77页

作者：董海涛张帅涛冯建强广西大学机械工程学院广西南宁530004

针对传统模拟伺服系统存在的通信实时性差、难以实现多轴同步控制等问题,提出一种将EtherCAT协议应用于传统模拟伺服系统的设计方案。以STM32和AX58100为核心,采用SPI从机扩展方法,结合DAC芯片等器件,设计了系统整体框架;根据分布时钟... 详细信息

针对传统模拟伺服系统存在的通信实时性差、难以实现多轴同步控制等问题,提出一种将EtherCAT协议应用于传统模拟伺服系统的设计方案。以STM32和AX58100为核心,采用SPI从机扩展方法,结合DAC芯片等器件,设计了系统整体框架;根据分布时钟同步模式和CiA402行规实现了多轴从站;采用TwinCAT3构建主站功能,在搭建的四轴伺服控制平台上进行了实验。在四轴EtherCAT通信分布时钟周期500μs时,报文刷新时间小于10μs,实现了四轴S型曲线同步控制,该方案对于实现传统模拟伺服系统的网络化,具有一定的参考价值。

关键词： EtherCAT 模拟伺服系统 SPI DAC TwinCAT

Stability and band gap engineering of silica-confined lead halide perovskite nanocrystals under high pressure

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Geoscience Frontiers 2021年第2期12卷 957-963页

作者： Ruijing Fu Yaping Chen Lingrui Wang Zhiwei Ma Pengfei Lv Ying Song Songrui Yang Guanjun Xiao Bo Zou State Key Laboratory of Superhard Materials College of PhysicsJilin UniversityChangchun130012China Key Laboratory of Materials Physics of Ministry of Education School of Physics and EngineeringZhengzhou UniversityZhengzhou450001China

SiO_(2)is the major mineral substance in the upper mantle of the earth.Therefore,studies of the silica-coated materials under high-pressure are essential to explore the physical and chemical properties of the upper mantle.The silica-confined CsPbBr_(3)nanocrystals(NCs)have recently attracted much attention because of the improved photoluminescence(PL)quantum yield,owing to the protection of silica shell.However,it remains considerable interest to further explore the relationship between optical properties and the structure of CsPbBr_(3)@SiO_(2)NCs.We systemically studied the structural and optical properties of the CsPbBr_(3)@SiO_(2)NCs under high pressure by using diamond anvil cell(DAC).The discontinuous changes of PL and absorption spectra occurred at~1.40 GPa.Synchrotron X-ray diffraction(XRD)studies of CsPbBr_(3)@SiO_(2)NCs under high pressure indicated an isostructural phase transformation at about 1.36 GPa,owing to the pressure-induced tilting of the Pb-Br octahedra.The isothermal bulk moduli for two phases are estimated about 60.0 GPa and 19.2 GPa by fitting the equation of state.Besides,the transition pressure point of CsPbBr_(3)@SiO_(2)NCs is slightly higher than that of pristine CsPbBr_(3)NCs,which attributed to the buffer effect of coating silica shell.The results indicate that silica shell is able to enhance the stabilization without changing the relationship between optical properties and structure of CsPbBr_(3)NCs.Our results were fascinated to model the rock metasomatism in the upper mantle and provided a new‘lithoprobe’for detecting the upper mantle.

关键词： Core-shell Perovskite CsPbBr3@SiO2 nanocrystals DAC High pressure Isostructural phase transformation

A single channel,6-bit 410-MS/s 3bits/stage asynchronous SAR ADC based on resistive DAC

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Journal of Semiconductors 2015年第5期36卷 151-157页

作者：韩雪魏琦杨华中汪蕙 Division of Circuits and Systems Department of Electronic EngineeringTsinghua University

This paper presents a single channel,low power 6-bit 410-MS/s asynchronous successive approximation register analog-to-digital converter(SAR ADC) for ultrawide bandwidth(UWB) communication,prototyped in a SMIC 65-nm process.Based on the 3 bits/stage structure,resistive DAC,and the modified asynchronous successive approximation register control logic,the proposed ADC attains a peak spurious-free dynamic range(SFDR) of41.95 dB,and a signal-to-noise and distortion ratio(SNDR) of 28.52 dB for 370 MS/s.At the sampling rate of410 MS/s,this design still performs well with a 40.71-dB SFDR and 30.02-dB SNDR.A four-input dynamic comparator is designed so as to decrease the power consumption.The measurement results indicate that this SAR ADC consumes 2.03 mW,corresponding to a figure of merit of 189.17 fj/step at 410 MS/s.

关键词： ADC SAR DAC MS 异步电阻比特单声道

A capacitive DAC with custom 3-D 1-fF MOM unit capacitors optimized for fastsettling routing in high speed SAR ADCs

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Journal of Semiconductors 2015年第5期36卷 158-162页

作者：陈迟晓向济璇陈华斌许俊叶凡李宁任俊彦 State Key Laboratory of ASIC and System Fudan University

Asynchronous successive approximation register(SAR) analog-to-digital converters(ADC) feature high energy efficiency but medium performance.From the point of view of speed,the key bottleneck is the unit capacitor size.In this paper,a small size three-dimensional(3-D) metal-oxide-metal(MOM) capacitor is proposed.The unit capacitor has a capacitance of 1-fF.It shapes as an umbrella,which is designed for fast settling consideration.A comparison among the proposed capacitor with other 3-D MOM capacitors is also given in the paper.To demonstrate the effectiveness of the MOM capacitor,a 6-b capacitive DAC is implemented in TSMC 1P9 M 65 nm LP CMOS technology.The DAC consumes a power dissipation of 0.16 mW at the rate of 100 MS/s,excluding a source-follower based output buffer.Static measurement result shows that INL is less than ± 1 LSB and DNL is less than ±0.5 LSB.In addition,a 100 MS/s 9-bit SAR ADC with the proposed 3-D capacitor is simulated.

关键词：电容式电容器 MOM DAC 3-D SAR ADC 单元

A 6-bit 4 GS/s pseudo-thermometer segmented CMOS DAC

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半导体学报：英文版 2014年第6期35卷 123-127页

作者：宋毅珺李文渊 Institute of RF-& OE-ICs Southeast University

A 6-bit 4 GS/s, high-speed and power-efficient DAC for ultra-high-speed transceivers in 60 GHz band millimeter wave technology is presented. A novel pseudo-thermometer architecture is proposed to realize a good compromise between the fast conversion speed and the chip area. Symmetrical and compact floor planning and layout techniques including tree-like routing, cross-quading and common-centroid method are adopted to guarantee the chip is fully functional up to near-Nyquist frequency in a standard 0.18 m CMOS process. Post simulation results corroborate the feasibility of the designed DAC, which can perform good static and dynamic linearity without calibration. DNL errors and INL errors can be controlled within0.28 LSB and0.26 LSB, respectively. SFDR at4 GHz clock frequency for a 1.9 GHz near-Nyquist sinusoidal output signal is 40.83 dB and the power dissipation is less than 37 mW.

关键词： DAC 温度计 CMOS GS 奈奎斯特频率毫米波技术分段芯片面积

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一种用于前台校准的8位高线性度DAC

微电子学 2018年第2期48卷 156-161,166页

作者：邓红辉周福祥付年华付振达合肥工业大学微电子设计研究所合肥230009

设计了一种用于12位折叠插值ADC前台校准的高线性度DAC。该DAC包括电流源、开关电路、译码电路和电流-电压转换器。电流-电压转换器采用带共模反馈和增益提高技术的运放,具有高的共模抑制比和高的输出线性度。电流源的版图设计中考虑了... 详细信息

设计了一种用于12位折叠插值ADC前台校准的高线性度DAC。该DAC包括电流源、开关电路、译码电路和电流-电压转换器。电流-电压转换器采用带共模反馈和增益提高技术的运放,具有高的共模抑制比和高的输出线性度。电流源的版图设计中考虑了电流源匹配特性,提出了"V"型布局方案,有效抑制其梯度误差和对称误差,提高了DAC转换线性度。在TSMC 0.18μm CMOS工艺下对DAC进行仿真。结果表明,当输入信号频率为4.101 5 MHz、采样频率为25MHz时,DAC的有效位数达到7.97位。

关键词： DAC 单位电流源电流-电压转换器 “V”型布局