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An IEEE 1149.x Embedded Test Coprocessor

Circuits and Systems 2014年第7期5卷 170-180页

作者： Ukbagiorgis Iyasu Gebremeskel José Manuel Martins Ferreira Faculty of Technology and Maritime Sciences Buskerud and Vestfold University College Kongsberg Norway

This paper describes a microprogrammed architecture for an embedded coprocessor that is able to control IEEE 1149.1 to IEEE 1149.7 test infrastructures, and explains how to expand the supported test command set. The coprocessor uses a fast simplex link (FSL) channel to interface a 32-bit MicroBlaze CPU, but it can work with any microprocessor core that accepts this simple FIFO-based interface method. The implementation cost (logic resource usage for a Xilinx Spartan-6 FPGA) and the performance data (operating frequency) are presented for a test command set comprising two parts: 1) the full IEEE 1149.1 structural test operations;2) a subset of IEEE 1149.7 operations selected to illustrate the implementation of advanced scan formats.

关键词： Built-In Test Boundary-Scan Embedded coprocessors MicroBlaze IEEE 1149.1 IEEE 1149.7

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Automatic Instruction Generation for Application Specific Co-processor

Automatic Instruction Generation for Application Specific Co...

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2005 6th International Conference on ASIC

作者： Shengtian Sang Xiaoming Li Yizheng Ye Microelectronics Center Harbin Institute of Technology

＜正＞By extending the baseline processor with application specific instructions,an application specific co-processor can meet the computational demands of the application. Working with the traditional co-processor interface,it doesn’t require the extensible processor core and has least impact on the existing hardware and *** paper proposes a framework for design space exploration and automatic co-processor instructions generation,in which application profiling,instruction identification and evaluation proceed seamlessly and *** optimal instruction set of the co-processor under given constraints is automatically generated from the source code of the *** demonstrate the effectiveness of the method we generate the instruction set of a SPARC V8 co-processor for a VoIP *** experiment gives promising results with the speedup of factor 2.3.

关键词： coprocessors Application software Hardware Space exploration Process design Computer aided instruction Software design Microelectronics Multimedia communication Multimedia systems

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Framework of Converting C++ Class to Hardware

Framework of Converting C++ Class to Hardware

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Zhao Xueming Zhou Xuegong Wang Lingli* State Key Laboratory of ASIC & System Fudan University Shanghai 201203 P. R. China State Key Laboratory of ASIC ＆ System Fudan University

In recent SOPC （System on Programmable Chip） design, a system becomes very complex and the cost of modifying the design during the development becomes very expensive. Based on the technology of the C to HDL （Hardware Description Language）, we propose a framework to convert C++ class to hardware, which can be used to cope with the change of design requirement during the development period. Within this framework, software and hardware components can be switched to each other easily, and can be reused between different projects as an object-oriental component.

关键词： [IEEE Keyword]Joining processes Hardware design languages Field programmable gate arrays System-on-a-chip coprocessors Software Hardware

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