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Design of a passive UHF RFID tag for the ISO18000-6C protocol

Journal of Semiconductors 2011年第5期32卷 124-129页

作者：王耀文光俊毛伟何艳莉朱学勇 RFIC Laboratory CICS School of Communication and Information EngineeringUniversity of Electronic Science and Technology of China

This paper presents a new fully integrated wide-range UHF passive RFID tag chip design that is compatible with the ISO18000-6C protocol. In order to reduce the die area, an ultra-low power CMOS voltage regulator without resistors and an area-efficient amplitude shift keying demodulator with a novel adaptive average generator are both adopted. A low power clock generator is designed to guarantee the accuracy of the clock under 4-4%. As the clock gating technology is employed to reduce the power consumption of the baseband processor, the total power consumption of the tag is about 14μW with a sensitivity of -9.5 dBm. The detection distance can reach about 5 m under 4 W effective isotropic radiated power. The whole tag is fabricated in TSMC 0.18μm CMOS technology and the chip size is 880 × 880μm^2.

关键词： ISO 18000-6C UHF RFID tag voltage regulator clock gating

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An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

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Computers, Materials & Continua 2022年第7期72卷 481-495页

作者： Rajkumar Sarma Cherry Bhargava Ketan Kotecha Department of Electrical&Electronics Engineering Faculty of Engineering&TechnologyJain(Deemed-to-be-University)Ramanagar562112KarnatakaIndia Symbiosis Institute of Technology Symbiosis International(Deemed University)LavalePune412115India Symbiosis Centre for Applied Artificial Intelligence Symbiosis International(Deemed University)LavalePune412115India

In the era of digital signal processing,like graphics and computation systems,multiplication-accumulation is one of the prime operations.A MAC unit is a vital component of a digital system,like different Fast Fourier Transform(FFT)algorithms,convolution,image processing algorithms,*** the domain of digital signal processing,the use of normalization architecture is very *** main objective of using normalization is to performcomparison and shift *** this research paper,an evolutionary approach for designing an optimized normalization algorithm is proposed using basic logical blocks such as Multiplexer,Adder *** proposed normalization algorithm is further used in designing an 8×8 bit Signed Floating-Point Multiply-Accumulate(SFMAC)*** the SFMAC can accept an 8-bit significand and a 3-bit exponent,the input to the said architecture can be somewhere between−(7.96872)_(10) to+(7.96872)_(10).The proposed architecture is designed and implemented using the Cadence Virtuoso using 90 and 130 nm technologies(in Generic Process Design Kit(GPDK)and Taiwan Semiconductor Manufacturing Company(TSMC),respectively).To reduce the power consumption of the proposed normalization architecture,techniques such as“block enabling”and“clock gating”are used *** to the analysis done on Cadence,the proposed architecture uses the least amount of power compared to its current predecessors.

关键词： Data normalization cadence virtuoso signed-floating-point MAC evolutionary optimized algorithm block enabling clock gating

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Design and implementation of a DSP with multi-level low power strategies for cochlear implants

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High Technology Letters 2009年第2期15卷 141-146页

作者：麦宋平 Zhang Chun Chao Jun Wang Zhihua Department of Electronic Engineering Tsinghua University Beijing 100084 P.R. China Institute of Microelectronics Tsinghua University Beijing 100084 P.R. China

This paper presents the design and implementation of a low power digital signal processor （THUCIDSP-1 ） targeting at application for cochlear implants. Multi-level low power strategies including algorithm optimization, operand isolation, clock gating and memory partitioning are adopted in the processor design to reduce the power consumption. Experimental results show that the complexity of the Continuous Interleaved Sampling （CIS） algorithm is reduced by more than 80 % and the power dissipation of the hardware alone is reduced by about 25% with the low power methods. The THUCIDSP-1 prototype, fabricated in 0.18-μm standard CMOS process, consumes only 1.91 mW when executing the CIS algorithm at 3 MHz.

关键词： digital signal processor (DSP) cochlear implant (CI) low power algorithm optimization operand isolation clock gating memory partitioning

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A New clock Gated Flip Flop for Pipelining Architecture

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Circuits and Systems 2016年第8期7卷 1361-1368页

作者： Krishnamoorthy Raja Siddhan Saravanan Excel Engineering College Komarapalayam India Muthayammal Engineering College Rasipuram India

The objective of the work is to design a new clock gated based flip flop for pipelining architecture. In computing and consumer products, the major dynamic power is consumed in the system’s clock signal, typically about 30% to 70% of the total dynamic (switching) power consumption. Several techniques to reduce the dynamic power have been developed, of which clock gating is predominant. In this work, a new methodology is applied for gating the Flip flop by which the power will be reduced. The clock gating is employed to the pipelining stage flip flop which is active only during valid data are arrived. The methodology used in project named Selective Look-Ahead clock gating computes the clock enabling signals of each FF one cycle ahead of time, based on the present cycle data of those FFs on which it depends. Similarly to data-driven gating, it is capable of stopping the majority of redundant clock pulses. In this work, the circuit implementation of the various blocks of data driven clock gating is done and the results are observed. The proposed work is used for pipelining stage in microprocessor and DSP architectures. The proposed method is simulated using the quartus for cyclone 3 kit.

关键词： Selective Look Ahead clock gating clock gating clock Networks Dynamic Power Reduction

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An Improved Power Efficient clock Pulsed D Flip-flop Using Transmission Gate

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Journal of Electronic & Information Systems 2023年第1期5卷 26-35页

作者： B.Syamala M.Thamarai Electronics and Communication Engineering Sri Vasavi Engineering CollegeAP534101India

Recent digital applications will require highly efficient and high-speed gadgets and it is related to the minimum delay and power *** proposed work deals with a low-power clock pulsed data flip-flop(D flip-flop)using a transmission *** accomplish a power-efficient pulsed D flip-flop,clock gating is *** gated clock reduces the unnecessary switching of the transistors in the circuit and thus reduces the dynamic power *** clock gating approach is employed by using an AND gate to disrupt the clock input to the circuit as per the control signal called *** to this process,the clock gets turned off to reduce power consumption when there is no change in the *** proposed transmission gate-based pulsed D flip-flop’s performance with clock gating and without clock gating circuit is *** proposed pulsed D flip-flop power consumption is 1.586μw less than the without clock gated ***,the authors have designed a 3-bit serial-in and parallel-out shift register using the proposed D flip-flop and analyzed the *** Electronic Design Automation tool is used to simulate all the circuits with 45 nm technology.

关键词： Pulsed D flip-flop clock gating Low power Shift register Transmission gate

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Based on Prospective Dynamic Frequency Scale Power Optimize Method for Multi-Cores Processor’s I/O System

Based on Prospective Dynamic Frequency Scale Power Optimize ...

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2012 National Conference on Information Technology and Computer Science

作者： Guo Yufeng School of Computer Science National University of Defense Technology Changsha,China

Power problem has been one of the most restricting development barriers of processor.I/O system power is an import part of the processor’s *** paper aims at I/O dynamic power of multi-cores processor,and put forwards a prospective dynamic frequency scale with clock gating power optimize *** experimental results show that the method which we put forward can greatly reduce the dynamic power of I/O system.

关键词： Multi-Cores Processor Dynamic Power Prospective Dynamic Frequency Scale clock gating

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