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A Novel Self-adaptive circuit design Technique Based on Evolvable Hardware

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International Journal of Automation and computing 2020年第5期17卷 744-751页

作者： Jun-Bin Zhang Jin-Yan Cai Ya-Feng Meng Tian-Zhen Meng Department of Electronic and Optical Engineering Mechanical Engineering CollegeShijiazhuang 050003China

Since traditional fault tolerance methods of electronic systems are based on redundant fault tolerance technique,and their structures are fixed when circuits are designed,the self-adaptive ability is *** order to solve these problems,a novel circuit self-adaptive design technique based on evolvable hardware(EHW)is *** features robustness,self-organization and *** can be adapted to a complex environment through dynamic configuration of the *** this paper,the proposed technique *** consumption of hardware resources and the number of convergence iterations *** effectiveness and superiority of the proposed technique are *** designed circuit has the ability of resistible redundant-state interference(RRSI).The proposed technique has a broad application prospect,and it has great significance.

关键词： circuit design self-adaptive design redundant fault tolerance technique evolvable hardware(EHW) evolutionary algorithms(EA)

A fuzzy-logic-based approach to accurate modeling of a double gate MOSFET for nanoelectronic circuit design

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Journal of Semiconductors 2012年第9期33卷 43-49页

作者： F.Djeffal A.Ferdi M.Chahdi LEA Department of ElectronicsUniversity of Batna05000 BatnaAlgeria LEPCM Department of ElectronicsUniversity of Batna05000 BatnaAlgeria

The double gate （DG） silicon MOSFET with an extremely short-channel length has the appropriate fea- tures to constitute the devices for nanoscale circuit design. To develop a physical model for extremely scaled DG MOSFETs, the drain current in the channel must be accurately determined under the application of drain and gate voltages. However, modeling the transport mechanism for the nanoscale structures requires the use of overkill meth- ods and models in terms of their complexity and computation time （self-consistent, quantum computations ）. Therefore, new methods and techniques are required to overcome these constraints. In this paper, a new approach based on the fuzzy logic computation is proposed to investigate nanoscale DG MOSFETs. The proposed approach has been implemented in a device simulator to show the impact of the proposed approach on the nanoelectronic cir- cuit design. The approach is general and thus is suitable for any type ofnanoscale structure investigation problems in the nanotechnology industry.

关键词： nanoscale circuit DG MOSFET fuzzy modelling computational cost circuit design

Time Characteristic Analysis and circuit design of External Interface of Embedded System

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Time Characteristic Analysis and Circuit Design of External ...

design of a DTCTGAL circuit and its application

The 7th International Conference on Computer-Aided Industrial design and Conceptual design (CAID&CD’2006)

作者： Pu Xiao-chuan Jiang Lie-hui Zhao Qiu-xia He Hong-qi Pu Xiao-chuan the Computer Science and Technology Department Institute of Information Engineering Information Engineering University

Citing the Ethernet and USB interface design of two microcontrollers, this paper emphasized the deeply analyzing and comparing of their external interface time characteristic, and presented the precise design scheme of interface circuit , and furthermore, discussed the universal ways and techniques of the external interface circuit design of Embedded System.

关键词： Embedded System external interface externa component time characteristic analysis circuit design

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Journal of Semiconductors 2009年第11期30卷 103-108页

作者：汪鹏君李昆鹏梅凤娜 Institute of circuits and Systems Ningbo University

By research on the switch-signal theory for multiple-valued logic circuits, the theory of three essential elements and the principle of adiabatic circuits, a design scheme for a double power clock ternary clocked transmission gate adiabatic logic （DTCTGAL） circuit is presented. The energy injection and recovery can be conducted by the bootstrapped NMOSFET, which makes the circuit maintain the characteristics of energy recovery as well as multiple-valued input and output. An XOR/XNOR circuit based on DTCTGAL is also presented using this design scheme. Finally, using the parameters of a TSMC 0.25μm CMOS device, PSPICE simulation results indicate that the proposed circuits have correct logic and significant low power characteristics.

关键词： multiple-valued logic adiabatic XOR/XNOR low power circuit design

design of replica bit line control circuit to optimize power for SRAM

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Journal of Semiconductors 2016年第12期37卷 70-75页

作者：汪鹏君周可基张会红龚道辉 Institute of circuits and Systems Ningbo University

A design of a replica bit line control circuit to optimize power for SRAM is proposed. The proposed design overcomes the limitations of the traditional replica bit line control circuit, which cannot shut off the word line in time. In the novel design, the delay of word line enable and disable paths are balanced. Thus, the word line can be opened and shut off in time. Moreover, the chip select signal is decomposed, which prevents feedback oscillations caused by the replica bit line and the replica word line. As a result, the switch power caused by unnec- essary discharging of the bit line is reduced. A 2-kb SRAM is fully custom designed in an SMIC 65-nm CMOS process. The traditional replica bit line control circuit and the new replica bit line control circuit are used in the designed SRAM, and their performances are compared with each other. The experimental results show that at a supply voltage of 1.2 V, the switch power consumption of the memory array can be reduced by 53.7%.

关键词： low power static random access memory (SRAM) replica bit line control circuit circuit design

design OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC circuit

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Journal of Electronics(China) 2007年第2期24卷 225-231页

作者： Wang Pengjun Yu Junjun Institute of circuits and Systems Ningbo University Ningbo 315211 China

First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.

关键词： circuit design Two-phase sinusoidal power clock Clock generator Clocked Transmission Gate Adiabatic Logic (CTGAL) circuit

design OF LIGHTWEIGHT PUF circuit BASED ON SELECTABLE CROSS-COUPLED INVERTERS

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Journal of Electronics(China) 2014年第6期31卷 513-518页

作者： Zhang Xuelong Li Jianrui Wang Pengjun Zhang Yuejun Institute of circuits and Systems Ningbo University

By analyzing the principle of process variations, a lightweight Physical Unclonable Function （PUF） circuit based on selectable cross-coupled inverters is proposed in this paper. Firstly, selectable cross-coupled inverters are chosen for two delay paths. Simultaneously, the circuit takes challenge signal to control each delay path. The PUF cell circuit is implemented in Semiconductor Manufacturing International Corporation （SMIC） 65 nm CMOS technology and the layout area is 2.94μm × 1.68μm. Then the 64-bit PUF circuit is achieved with the cascade connection of cell circuits. The simulation results show that the randomness is 49.4% and the reliability is 96.5%. Compared to the other works, this PUF circuit improves the encrypt performance and greatly reduces the area.

关键词： Lightweight Physical Unclonable Punction (PUF) Cross-coupled inverter circuit design

design of Digital circuit Experiment Course Based on FPGA

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World Journal of Engineering and Technology 2021年第2期9卷 346-356页

作者： Lei Zhao Electronic Experimental Center Chengdu University of Information Technology Chengdu China

With the development of integrated circuit, the content of digital circuit experiment course is constantly updated. In order to keep up with the development trend of the Times and make students’ professional knowledge meet the needs of the industry, the school adopts the FPGA experimental platform to carry out teaching reform from the two aspects of platform and experiment, and carry out reasonable experimental planning to enrich the experimental content. In this paper, the traditional knowledge points of logic algebra, trigger, timer, counter, decoder and digital tube are organically combined, and the digital clock system is designed and realized. The practice shows that the combination of modern design method and traditional digital circuit teaching method can play a good teaching effect. In this way, students can also fully learn, understand and skillfully use the new technology in the experiment, and in the process of building a comprehensive understanding of digital circuits.

关键词： Digital circuit FPGA circuit design Software Simulation Digital Clock System

design of Ternary Adiabatic T-operation circuit Based on the Theory of Three Essential circuit Elements

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Design of Ternary Adiabatic T-operation Circuit Based on the...