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Chip Design of Li-Ion Battery Charger Operating in Constant-Current/Constant-Voltage Modes

Journal of Semiconductors 2007年第7期28卷 1030-1035页

作者：陈琛何乐年浙江大学超大规模集成电路设计研究所杭州310027

A design for a Li-ion battery charger IC that can operate in a constant current-constant voltage （CC- CV） charge mode is proposed. In the CC-CV charge mode,the charger IC provides a constant charging current at the beginning, and then the charging current begins to decrease before the battery voltage reaches its final value. After the battery voltage reaches its final value and remains constant,the charging current is further reduced. This approach prevents charging the battery with full current near its saturated voltage,which can cause heating. The novel design of the core of the charger IC realizes the proposed CC-CV charge mode. The chip was implemented in a CSMC 0.6μm cmos mixed signal process. The experimental results verify the realization of the proposed CC- CV charge mode. The voltage of the battery after charging is 4. 1833V.

关键词： Li-ion battery charger constant current-constant voltage charge modes cmos analog circuit

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Rail-to-rail op-amp with constant transconductance,SR and gain

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Journal of Southeast University(English Edition) 2008年第2期24卷 163-167页

作者：常昌远李弦姚建楠李娟东南大学集成电路学院南京210096 东南大学电子科学与工程学院南京210096

A novel general-purpose low-voltage rail-to-rail cmos （ complementary metal-oxide-semiconductor transistor ） operational amplifier （op-amp）is introduced, which obtains constant transconductance, slew rate and constant high gain over the entire input common mode voltage range. The proposed scheme has the potential for applications in deep submicrometer technology, as the operation of the circuit does not exclusively rely on the square-law or the linear-law of transistors. The scheme is compact and suitable for applications as VLSI cell. The rail-to- rail op-amp has been implemented in DPDM 0. 6 μm mixedsignal process. The simulations show that in the entire range of input common mode voltage, the variations in transconductance, SR and gain are 1%, 2. 3%, 1.36 dB, respectively. Based on this, the layout and tape-out are carded out. The area of layout is 0. 072 mm^2. The test results are basically consistent with the circuit simulation.

关键词： cmos analog circuit op-amp rail-to-rail constant transconductance constant slew rate constant gain

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