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Frontiers of Computer Science 2022年第3期16卷 41-52页

作者： Dunbo ZHANG Chaoyang JIA Li SHEN School of Computer National University of Defense TechnologyChangsha 410000China

GPUs are widely used in modem high-performance computing *** reduce the burden of GPU programmers,operating system and GPU hardware provide great supports for shared virtual memory,which enables GPU and CPU to share the same virtual address ***,the current SIMT execution model of GPU brings great challenges for the virtual-physical address translation on the GPU side,mainly due to the huge number of virtual addresses which are generated simultaneously and the bad locality of these virtual ***,the excessive TLB accesses increase the miss ratio of *** an attractive solution,Page Walk Cache(PWC)has received wide attention for its capability of reducing the memory accesses caused by TLB ***,the current PWC mechanism suffers from heavy redundancies,which significantly limits its *** this paper,we first investigate the facts leading to this issue by evaluating the performance of PWC with typical GPU *** find that the repeated L4 and L3 indices of virtual addresses increase the redundancies in PWC,and the low locality of L2 indices causes the low hit ratio in *** on these observations,we propose a new PWC structure,namely Compressed Page Walk Cache(CPWC),to resolve the redundancy burden in current *** CPWC can be organized in either direct-mapped mode or set-associated *** results show that CPWC increases by 3 times over TPC in the number of page table entries,increases by 38.3%over PWC in L2 index hit ratio and reduces by 26.9%in the memory accesses of page *** average memory accesses caused by each TLB miss is reduced to ***,the average IPC can improve by 25.3%.

关键词： GPU shared virtual memory address translation PWC

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System Architecture Design of PCIe Root Complex Based on SOPC 36

System Architecture Design of PCIe Root Complex Based on SOP...

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第36届中国控制会议

作者： Yufeng Liu Degang Xu Haiming Cai Chunhua Yang College of Information Science and Engineering Central South University

ISBN: (纸本)9781538629185

PCIe bus is widely applied because of its high-bandwidth,high reliability and low cost *** on PCIe root complex architecture based on FPGA begin to receive ***,current methods are usually expensive,code closure and poor flexibility.A new open source PCIe root system architecture based on Xilinx SOPC platform is proposed in this *** system is mainly composed of AXI-PCIe bridge,,AXI interconnect,processing subsystem and DDR3 *** processing system runs the embedded Linux operating system for controlling and management *** AXI-PCIe bridge communicates with the specific PCIe endpoint device and provides the conversion logic for the PCIe domain address and the AXI domain *** are connected by high performance AXI *** paper uses the gigabit ethernet card and network bandwidth testing tools to verify the proposed hardware and software design *** architecture of this approach has the advantages of simple structure,powerful performance and easy expansion,which provides a feasible solution for new high-performance servers and large-scale PLC systems.

关键词： PCIe root complex SOPC processing system AXI-PCIe bridge address translation

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Superpage-Friendly Page Table Design for Hybrid Memory Systems

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国际计算机前沿大会会议论文集 2020年第1期 623-641页

作者： Xiaoyuan Wang Haikun Liu Xiaofei Liao Hai Jin National Engineering Research Center for Big Data Technology and System Huazhong University of Science and TechnologyWuhan 430074China Service Computing Technology and System Lab Huazhong University of Science and TechnologyWuhan 430074China Cluster and Grid Computing Lab Huazhong University of Science and TechnologyWuhan 430074China School of Computer Science and Technology Huazhong University of Science and TechnologyWuhan 430074China

Page migration has long been adopted in hybrid memory systems comprising dynamic random access memory(DRAM)and non-volatile memories(NVMs),to improve the system performance and energy ***,page migration introduces some side effects,such as more translation lookaside buffer(TLB)misses,breaking memory contiguity,and extra memory accesses due to page table *** this paper,we propose superpagefriendly page table called SuperPT to reduce the performance overhead of serving TLB *** leveraging a virtual hashed page table and a hybrid DRAM allocator,SuperPT performs address translations in a flexible and efficient way while still remaining the contiguity within the migrated pages.

关键词： Page table Hybrid memory system Page migration Multiple page sizes address translation

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A Wireless LAN Bridging Solution Based on Campus Network

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Journal of Electronic Science and Technology of China 2005年第1期3卷 14-17页

作者：刘航毛玉明 School of Communication and Information Engineering UESTC Chengdu 610054 China

This paper presents a creative wireless LAN (WLAN) bridging solution, concentrating on the overall realization of a well designed interconnection. This solution integrates effective traffic insulation, intended access control, and required address translation without interfering with the vested interest of internet service provider (ISP). The specific solution can be widely applied on the campus-dorm (off campus)-ISP internetworking mode, where it is hard to implement wired link between campus network and dorm network in terms of cost and existing environmental constraints.

关键词： WLAN bridging wireless link traffic insulation access control address translation

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