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Accurate and fast table look-up models for leakage current analysis in 65nm CMOS technology

Journal of Semiconductors 2009年第2期30卷 42-47页

作者：薛冀颖李涛余志平 Institute of Microelectronics Tsinghua University

Novel physical models for leakage current analysis in 65 nm technology are proposed. Taking into consideration the process variations and emerging effects in nano-scaled technology, the presented models are capable of accurately estimating the subthreshold leakage current and junction tunneling leakage current in 65 nm technology. Based on the physical models, new table look-up models are developed and first applied to leakage current analysis in pursuit of higher simulation speed. Simulation results show that the novel physical models are in excellent agreement with the data measured from the foundry in the 65 nm process, and the proposed table look-up models can provide great computational efficiency by using suitable interpolation techniques. Compared with the traditional physical-based models, the table look-up models can achieve 2.5X speedup on average on a variety of industry circuits.

关键词： leakage current 65 nm technology table look-up model interpolation

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A 1G-cell floating-gate NOR flash memory in 65 nm technology with 100 ns random access time

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Science China(Information Sciences) 2015年第4期58卷 158-165页

作者： LIU LiFang WU Dong LIU XueMei HUO ZongLiang LIU Ming PAN LiYang Institute of Microelectronics University of Tsinghua Tsinghua National Laboratory for Information Science and technology Laboratory of Nano-Fabrication and Novel Devices Integrated technology Institute of MicroelectronicsChinese Academy of Sciences

A 1G-cell NOR flash memory chip has been designed and fabricated successfully with 65 nm technology. To compromise the array efficiency and chip speed, the paper establishes an array model including parasitics of the whole array, and optimizes the sector structure as 512 wordlines(WLs) and 4096 bitlines(BLs).Furthermore, by adding other models of long and thin metal lines, we have analyzed the speed of critical circuit nodes. As a result, the agreement of WL delay between simulation and measurement verifies the accuracy of the array model and lines models. The test results indicate that the chip achieves random access time of 100 ns and page read time of 25 ns under 3.3 V voltage supply.

关键词： NOR flash memory giga-level 65 nm technology array efficiency high speed

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