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数字锁相环技术在恢复位时钟中的应用

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军民两用技术与产品 2004年第2期 39-41页

作者：李新昌吴嗣亮王旭北京理工大学电子工程系北京100081

详细介绍了如何在FPGA中利用VHDL语言实现超前滞后型数字锁相环,以便从位流数据中恢复出位时钟;并指出了其结构参数对于环路性能的影响。

关键词： FPGA VHDL语言数字锁相环位时钟恢复数字鉴相器

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维普期刊数据库

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A high precision time-to-digital converter based on multi-phase clock implemented within Field-Programmable-Gate-Array

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Nuclear Science and Techniques 2010年第2期21卷 123-128页

作者： CHEN Kai LIU Shubin AN Qi Key Laboratory of Technologies of Particle Detection ＆ Electronics Chinese Academy of Sciences Department of Modern Physics University of Seience and Technology of China Hefei 230026 China Anhui Key Laboratory of Physics Electronics Department of Modern Physics University of Science and Technology of China Hefei 230026 China

In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.

关键词：现场可编程门阵列时间数字转换器位时钟高精度抽头延迟线多相基础微分非线性

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