Virtual prototypes(VPs) are crucial in today's design flow. VPs are predominantly created in System C transaction-level modeling(TLM) and are leveraged for early software development and other system-level use cases. ...
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Virtual prototypes(VPs) are crucial in today's design flow. VPs are predominantly created in System C transaction-level modeling(TLM) and are leveraged for early software development and other system-level use cases. Recently, virtual prototyping has been introduced for the emerging RISC-V instruction set architecture(ISA) and become an important piece of the growing RISC-V ecosystem. In this paper, we present enhanced virtual prototyping solutions tailored for RISC-V. The foundation is an advanced open source RISC-V VP implemented in System C TLM and designed as a configurable and extensible *** scales from small bare-metal systems to large multi-core systems that run applications on top of the Linux operating system. Based on the RISC-V VP, this paper also discusses advanced VP-based verification approaches and open challenges. In combination, we provide for the first time an integrated and unified overview and perspective on advanced virtual prototyping for RISC-V.
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