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Discrete-time charge analysis for a digital RF charge sampling mixer

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Journal of Zhejiang University-Science C(Computers and Electronics) 2010年第4期11卷 307-314页

作者： Yun PAN Ning GE xiao-lang yan xiao-peng YU Institute of VLS1 Design Zhejiang University Hangzhou 310027 China Department of Electronic Engineering Tsinghua University Beijing 100084 China

This paper presents an approach for analyzing the key parts of a general digital radio frequency(RF) charge sampling mixer based on discrete-time charge *** cascade sampling and filtering stages are analyzed and expressed in theoretical *** effects of a pseudo-differential structure and CMOS switch-on resistances on the transfer function are addressed in *** DC-gain is restrained by using the pseudo-differential *** transfer gain is reduced because of the charge-sharing time constant when taking CMOS switch-on resistances into *** unfolded transfer gains of a typical digital RF charge sampling mixer are analyzed in different cases using this approach.A circuit-level model of the typical mixer is then constructed and simulated in Cadence SpectreRF to verify the *** work informs the design of charge-sampling,infinite impulse response(ⅡR) filtering,and finite impulse response(FIR) filtering *** discrete-time approach can also be applied to other multi-rate receiver systems based on charge sampling techniques.

关键词： Digital RF Charge sampling Discrete-time Pseudo-differential Switch-on resistance

A new via chain design method considering confidence level and estimation precision

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Journal of Zhejiang University-Science C(Computers and Electronics) 2012年第9期13卷 702-710页

作者： xiao-hua LUO Li-sheng CHEN Jiao-jiao ZHU xiao-lang yan Institute of VLSI Design Zhejiang UniversityHangzhou 310027China

For accurate prediction of via yield, via chains are usually fabricated on test chips to investigate issues about vias. To minimize the randomness of experiments and make the testing results more convincing, the confidence level and estimation precision of the via failure rate are investigated in this paper. Based on the Poisson yield model, the method of determining an adequate number of total vias is obtained using the law of large numbers and the de Moivre-Laplace theorem. Moreover, for a specific confidence level and estimation precision, the method of determining a suitable via chain length is proposed. For area minimization, an optimal combination of total vias and via chain length is further determined. Monte Carlo simulation results show that the method is in good accordance with theoretical analyses. Results of via failure rates measured on test chips also reveal that via chains designed using the proposed method has a better performance. In addition, the proposed methodology can be extended to investigate statistical significance for other failure modes.

关键词： Poisson yield model Via chain Via failure rate Confidence level Estimation precision

Regularized level-set-based inverse lithography algorithm for IC mask synthesis

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Journal of Zhejiang University-Science C(Computers and Electronics) 2013年第10期14卷 799-807页

作者： Zhen GENG Zheng SHI xiao-lang yan Kai-sheng LUO Institute of VLSI Design Zhejiang University

Inverse lithography technology(ILT)is one of the promising resolution enhancement techniques,as the advanced IC technology nodes still use the 193 nm light *** ILT,optical proximity correction(OPC)is treated as an inverse imaging problem to find the optimal solution using a set of mathematical *** all the algorithms for ILT,the level-set-based ILT(LSB-ILT)is a feasible choice with good production in ***,the manufacturability of the optimized mask is one of the critical issues in ILT;that is,the topology of its result is usually too complicated to *** put forward a new algorithm with high pattern fidelity called regularized LSB-ILT implemented in partially coherent illumination(PCI),which has the advantage of reducing mask complexity by suppressing the isolated irregular holes and protrusions in the edges generated in the optimization process.A new regularization term named the Laplacian term is also proposed in the regularized LSB-ILT optimization process to further reduce mask complexity in contrast with the total variation(TV)*** results show that the new algorithm with the Laplacian term can reduce the complexity of mask by over 40%compared with the ordinary LSB-ILT.

关键词： Inverse lithography technology Complexity Level set Regularization

SVM based layout retargeting for fast and regularized inverse lithography

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Journal of Zhejiang University-Science C(Computers and Electronics) 2014年第5期15卷 390-400页

作者： Kai-sheng LUO Zheng SHI xiao-lang yan Zhen GENG Institute of VLSI Design Zhejiang University

Inverse lithography technology(ILT),also known as pixel-based optical proximity correction(PB-OPC),has shown promising capability in pushing the current 193 nm lithography to its *** treating the mask optimization process as an inverse problem in lithography,ILT provides a more complete exploration of the solution space and better pattern fidelity than the traditional edge-based ***,the existing methods of ILT are extremely time-consuming due to the slow convergence of the optimization *** address this issue,in this paper we propose a support vector machine(SVM)based layout retargeting method for ILT,which is designed to generate a good initial input mask for the optimization process and promote the convergence *** by optimized masks of training layouts generated by conventional ILT,SVM models are learned and used to predict the initial pixel values in the‘undefined areas’of the new *** this process,an initial input mask close to the final optimized mask of the new layout is generated,which reduces iterations needed in the following optimization *** is another critical issue in ILT;however,the mask generated by our layout retargeting method is quite irregular due to the prediction inaccuracy of the SVM *** compensate for this drawback,a spatial filter is employed to regularize the retargeted mask for complexity *** implemented our layout retargeting method with a regularized level-set based ILT(LSB-ILT)algorithm under partially coherent illumination *** results show that with an initial input mask generated by our layout retargeting method,the number of iterations needed in the optimization process and runtime of the whole process in ILT are reduced by 70.8%and 69.0%,respectively.

关键词： Inverse lithography technology Optical proximity correction Layout retargeting Support vector machine

Efficient implementation of a cubic-convolution based image scaling engine

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Journal of Zhejiang University-Science C(Computers and Electronics) 2011年第9期12卷 743-753页

作者： Xiang WANG Yong DING Ming-yu LIU xiao-lang yan Institute of VLSI Design Zhejiang University Hangzhou 310027 China

In video applications, real-time image scaling techniques are often required. In this paper, an efficient implementation of a scaling engine based on 4×4 cubic convolution is proposed. The cubic convolution has a better performance than other traditional interpolation kernels and can also be realized on hardware. The engine is designed to perform arbitrary scaling ratios with an image resolution smaller than 2560× 1920 pixels and can scale up or down, in horizontal or vertical direction. It is composed of four fimctional units and five line buffers, which makes it more competitive than conventional architectures. A strict fixed-point strategy is applied to minimize the quantization errors of hardware realization. Experimental results show that the engine provides a better image quality and a comparatively lower hardware cost than reference implementations.

关键词： Cubic-convolution Hardware implementation Interpolation Engine

A parallel memory architecture for video coding

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Journal of Zhejiang University-Science A(Applied Physics & Engineering) 2008年第12期9卷 1644-1655页

作者： Jian-ying PENG xiao-lang yan De-xian LI Li-zhong CHEN Institute of VLSI Design Zhejiang University Hangzhou 310027 China

To efficiently exploit the performance of single instruction multiple data （SIMD） architectures for video coding, a parallel memory architecture with power-of-two memory modules is proposed. It employs two novel skewing schemes to provide conflict-free access to adjacent elements （8-bit and 16-bit data types） or with power-of-two intervals in both horizontal and vertical directions, which were not possible in previous parallel memory architectures. Area consumptions and delay estimations are given respectively with 4, 8 and 16 memory modules. Under a 0.18-pm CMOS technology, the synthesis results show that the proposed system can achieve 230 MHz clock frequency with 16 memory modules at the cost of 19k gates when read and write latencies are 3 and 2 clock cycles, respectively. We implement the proposed parallel memory architecture on a video signal processor （VSP）. The results show that VSP enhanced with the proposed architecture achieves 1.28× speedups for H.264 real-time decoding.

关键词： Single instruction multiple data (SIMD) Video coding Parallel memory Skewing scheme

A sparse matrix model-based optical proximity correction algorithm with model-based mapping between segments and control sites

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Journal of Zhejiang University-Science C(Computers and Electronics) 2011年第5期12卷 436-442页

作者： Bin LIN xiao-lang yan Zheng SHI Yi-wei yanG Institute of VLSI Design Zhejiang University Hangzhou 310027 China

Optical proximity correction (OPC) is a key step in modern integrated circuit (IC) *** quality of model-based OPC (MB-OPC) is directly determined by segment offsets after OPC ***,in conventional MB-OPC,the intensity of a control site is adjusted only by the movement of its corresponding segment;this scheme is no longer accurate enough as the lithography process *** the other hand,matrix MB-OPC is too time-consuming to become *** this paper,we propose a new sparse matrix MB-OPC algorithm with model-based mapping between segments and control *** put forward the concept of 'sensitive area'.When the Jacobian matrix used in the matrix MB-OPC is evaluated,only the elements that correspond to the segments in the sensitive area of every control site need to be calculated,while the others can be set to *** new algorithm can effectively improve the sparsity of the Jacobian matrix,and hence reduce the *** theoretical analysis and experiments show that the sparse matrix MB-OPC with model-based mapping is more accurate than conventional MB-OPC,and much faster than matrix MB-OPC while maintaining high accuracy.

关键词： Matrix sparsity Optical proximity correction (OPC) Convergence Segment Sensitive area

High throughput VLSI architecture for H.264/AVC context-based adaptive binary arithmetic coding(CABAC) decoding

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Journal of Zhejiang University-Science C(Computers and Electronics) 2013年第6期14卷 449-463页

作者： Kai HUANG De MA Rong-jie yan Hai-tong GE xiao-lang yan Institute of VLSI Design Zhejiang University State Key Laboratory of Computer Science Institute of SoftwareChinese Academy of Sciences Hangzhou C-Sky Micro-System Company

Context-based adaptive binary arithmetic coding(CABAC) is the major entropy-coding algorithm employed in H.264/*** this paper,we present a new VLSI architecture design for an H.264/AVC CABAC decoder,which optimizes both decode decision and decode bypass engines for high throughput,and improves context model allocation for efficient external memory *** on the fact that the most possible symbol(MPS) branch is much simpler than the least possible symbol(LPS) branch,a newly organized decode decision engine consisting of two serially concatenated MPS branches and one LPS branch is proposed to achieve better parallelism at lower timing path cost.A look-ahead context index(ctxIdx) calculation mechanism is designed to provide the context model for the second MPS branch.A head-zero detector is proposed to improve the performance of the decode bypass engine according to UEGk encoding *** addition,to lower the frequency of memory access,we reorganize the context models in external memory and use three circular buffers to cache the context models,neighboring information,and bit stream,respectively.A pre-fetching mechanism with a prediction scheme is adopted to load the corresponding content to a circular buffer to hide external memory *** results show that our design can operate at 250 MHz with a 20.71k gate count in SMIC18 silicon technology,and that it achieves an average data decoding rate of 1.5 bins/cycle.

关键词： H.264/AVC Context-based adaptive binary arithmetic coding(CABAC) Decoder VLSI

Scratch-concerned yield modeling for IC manufacturing involved with a chemical mechanical polishing process

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Journal of Zhejiang University-Science C(Computers and Electronics) 2012年第5期13卷 376-384页

作者： Jiao-jiao ZHU xiao-hua LUO Li-sheng CHEN Yi YE xiao-lang yan Institute of VLSI Design .Zhefiang UniversityHangzhou 310027China

In existing integrated circuit (IC) fabrication methods,the yield is typically limited by defects generated in the manufacturing *** fact,the yield often shows a good correlation with the type and density of the *** a result,an accurate defect limited yield model is essential for accurate correlation analysis and yield *** real defects exhibit a great variety of shapes,to ensure the accuracy of yield prediction,it is necessary to select the most appropriate defect model and to extract the critical area based on the defect *** the realistic outline of scratches introduced by the chemical mechanical polishing (CMP) process,we propose a novel scratch-concerned yield model.A linear model is introduced to model *** on the linear model,the related critical area extraction algorithm and defect density distribution are *** to higher correspondence with the realistic outline of scratches,the linear defect model enables a more accurate yield prediction caused by scratches and results in a more accurate total product yield prediction as compared to the traditional circular model.

关键词： Chemical mechanical polishing (CMP) Scratch Defect Yield model Critical area