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Computerised Gate Firing Control for 17-Level MLI using Staircase PWM

Computer Systems Science & Engineering 2023年第1期44卷 813-832页

作者： M.Geetha R.Vijayabhasker suresh seetharaman Department of Electronics and Communications Engineering Kalaignar Karunanidhi Institute of TechnologyCoimbatoreTamilnadu641402India Department of Electrical and Electronics Engineering Anna UniversityRegional Centre CoimbatoreTamilnadu641046India

A basic 7-level MLI topology is developed and the same is extended to the 9-level then further increased to *** developed structure minimizes the component’s count and size to draw out the system *** the various advantages of MLIs,efficiency and reliability play a major role since the usage of components is higher for getting a low Total Harmonics Distortion(THD)*** becomes a major challenge incorporated in boosting the efficiency without affecting the THD *** parametric observations are done and realized for the designed 9-level and 17-level MLI,being the Total Standing Voltage(TSV),efficiency,cost function per level count,and power *** respective parameters are compared with several existing and modern circuits and found to be effective in their performance.A novel single-phase 17-level asymmetrical Multi-Level Inverter(MLI)topology is developed to reduce the number of overall *** developed topology generates 17-levels by using unequal DC *** developed MLI is proved under various tests con-ducted experimentally for the various loads like resistive,inductive,and combinational loads.A detailed comparison is done on several factors and represented graphically ***,the proposed design provides a less TSV value is 6 V_(dc),efficiency is 94.21%and cost factor per level CF/L value for both values ofαis 2.01 and 2.05 and devices count with a low THD value 41.4%with respectively.

关键词： Inverters 9-level and 17-level MLI switches count load current voltages round-robin staircase PWM

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