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Looking into the future of Nanoelectronics in the Diversification Efficient Era

Science China(Information Sciences) 2016年第6期59卷 6-19页

作者： simon deleonibus Universit′es Grenoble Alpes CEA LETIMINATEC Campus

The linear scaling of CMOS has encountered, since its beginning, many hurdles which request new process modules, driven mainly by the maximization of energy efficiency. Fabrication at the sub 10 nm node level will request Intrinsic Variability approaching to zero. The rapid growth of mobile, multifunctional and autonomous systems is hardly demanding to reach Zero Power consumption. The solutions to integrate Thin Film based devices, architectures and systems in order to face these challenges are described.

关键词： CMOS thin films heterogeneous integration NEMS 3D integration sequential parallel zero intrinsic variability zero power systems

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Ultra-thin films and multigate devices architectures for future CMOS scaling

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Science China(Information Sciences) 2011年第5期54卷 990-1003页

作者： deleonibus simon CEA-LETI MINATEC Campus Grenoble France

The nanoelectronics industry is facing historical challenges to scale down CMOS devices to meet demands for low voltage, low power, high performance and increased functionality. Using new materials and devices architectures is necessary. HiK gate dielectrics and metal gates have been introduced and have shown their ability to reduce power consumption. Fully depleted ultra-thin SOI devices are a good alternative to bulk for low power applications. Multigate devices are the current goal in device architecture to increase MOSFET drivability, reduce power, and allow new opportunities for future applications. Thin film based solutions will be necessary in the future because of fundamental limitations on gate capacitance scaling and system integration requirements. Exploiting 3D device stacking via wafer bonding could be a good way to introduce new materials (HiK, strained Si, hybrid orientations, Ge, III-Vs, Carbon-based materials, graphene and CNTs, and functional molecules) and continue increasing integration density. Si based CMOS will be scaled beyond the ITRS as the System-on-Chip/Wafer Platform.

关键词： CMOSFETs silicon strain carbon germanium silicon on insulator technology FDSOI FinFET multigates nanowires wafer bonding 3D sequential integration

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