检索结果-南通市图书馆

Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip

Journal of Computer Science & Technology 2013年第1期28卷 54-71页

作者： Xiao-Hang Wang Peng Liu Mei Yang maurizio palesi Ying-Tao Jiang Michael C Huang Intelligent Chips and Systems Research Centre Guangzhou Institute of Advanced Technology Chinese Academy of Sciences Guangzhou 511458 China Department of Information Science and Electronic Engineering Zhejiang University Hangzhou 310027 China Department of Electrical and Computer Engineering University of Nevada Las Vegas Nevada U.S.A. Faculty of Engineering Kore University Catania Italy Department of Electrical and Computer Engineering University of Rochester Rochester New York U.S.A.

3-D Networks-on-Chip （NoC） emerge as a potent solution to address both the interconnection and design complexity problems facing future Multiprocessor System-on-Chips （MPSoCs）. Effective run-time mapping on such 3-D NoC-based MPSoCs can be quite challenging, as the arrival order and task graphs of the target applications are typically not known a priori, which can be further complicated by stringent energy requirements for NoC systems. This paper thus presents an energy-aware run-time incremental mapping algorithm （ERIM） for 3-D NoC which can minimize the energy consumption due to the data communications among processor cores, while reducing the fragmentation effect on the incoming applications to be mapped, and simultaneously satisfying the thermal constraints imposed on each incoming application. Specifically, incoming applications are mapped to cuboid tile regions for lower energy consumption of communication and the minimal routing. Fragment tiles due to system fragmentation can be gleaned for better resource utilization. Extensive experiments have been conducted to evaluate the performance of the proposed algorithm ERIM, and the results are compared against the optimal mapping algorithm （branch-and-bound） and two heuristic algorithms （TB and TL）. The experiments show that ERIM outperforms TB and TL methods with significant energy saving （more than 10%）, much reduced average response time, and improved system utilization.

关键词： energy efficiency Networks-on-Chip multiprocessor System-on-Chips run-time incrementa] mapping

来源：

维普期刊数据库

同方期刊数据库评论

在线全文

学校读者我要写书评

暂无评论

欢迎您,

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

在线全文

请选择保存的检索档案：

请选择收藏分类：

通借通还

欢迎您,

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

在线全文

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：