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A Coding Scheme for Noisy Image Based on Layer Segmentation

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Chinese Journal of Electronics 2016年第4期25卷 700-705页

作者： LI Tao TIAN Xin xiong chengyi TIAN Jinwen Nanjing Research Institute of Electronics Technology Wuhan University South–Central University for Nationalities Huazhong University of Science and Technology

Heavy noises distribute in the images when imaging in a poor *** randomness of noises makes pixels distributing singularly,which weakens the1-D piecewise smooth property of original ***,wavelets-based compression method no longer works *** this paper,a layer segmentation based compression scheme is proposed for gray *** textures and some high frequency noises are described in a high frequency layer while the coarse part of the image is described in the low frequency *** high frequency layer is represented by a joint dictionary,and the low frequency layer is coded with the traditional *** proposed scheme is tested on nature images and synthetic *** results show that the proposed scheme achieves better rate-distortion performance compared with several competing compression ***,further degradation of edges is avoided by the proposed compression scheme.

关键词： Image coding Noisy image model Sparse representation Edge detection

High performance word level sequential and parallel coding methods and architectures for bit plane coding

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Science in China(Series F) 2008年第4期51卷 337-351页

作者： xiong chengyi TIAN JinWen LIU Jian College of Electronic Information Engineering South-Central University for Nationalities Wuhan 430074 China Institute of Pattern Recognition & Artificial Intelligence Key Laboratory of Education Ministry for Image Processing and Intelligent Control Huazhong University of Science & Technology Wuhan 430074 China

This paper introduced a novel high performance algorithm and VLSI architectures for achieving bit plane coding （BPC） in word level sequential and parallel mode. The proposed BPC algorithm adopts the techniques of coding pass prediction and parallel ＆ pipeline to reduce the number of accessing memory and to increase the ability of concurrently processing of the system, where all the coefficient bits of a code block could be coded by only one scan. A new parallel bit plane architecture （PA） was proposed to achieve word-level sequential coding. Moreover, an efficient high-speed architecture （HA） was presented to achieve multi-word parallel coding. Compared to the state of the art, the proposed PA could reduce the hardware cost more efficiently, though the throughput retains one coefficient coded per clock. While the proposed HA could perform coding for 4 coefficients belonging to a stripe column at one intra-clock cycle, so that coding for an NxN code-block could be completed in approximate N2/4 intra-clock cycles. Theoretical analysis and experimental results demonstrate that the proposed designs have high throughput rate with good performance in terms of speedup to cost, which can be good alternatives for low power applications.

关键词： bit plane coding high performance word-level sequential multi-word parallel

Fast Implementation for the Singular Value and Eigenvalue Decomposition Based on FPGA

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Chinese Journal of Electronics 2017年第1期26卷 132-136页

作者： ZHANG Shuiping TIAN Xin xiong chengyi TIAN Jinwen MING Delie School of Computer Science and Engineering Wuhan Institute of Technology School of Electronic Information Wuhan University School of Electronic and Information Engineering South-central University for Nationalities School of Automation Huazhong University of Science and Technology

A fast and efficient hardware implementation for computing the Singular value decomposition(SVD) and Eigenvalue decomposition(EVD) is *** that the SVD and EVD are complex and expensive operations, to achieve high performance with low computing complexity, our approach takes full advantage of the combination of parallel and sequential computation, which can increase efficiently the hardware utilization. Besides, regarding to EVD, we propose a hardware solution of a simplified Coordinate rotation digital computer(CORDIC)-like algorithm which can obtain higher speed. The performance analysis and comparison results show that the proposed methods can be realized on Filedprogrammable gate arrays(FPGAs) with less computation time by using systolic array. It will be shown that the proposed implementation could be an efficient alternative for real-time applications.

关键词： SVD EVD Jacobi CORDIC FPGA

局部特征增强的磁Transformer重构

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中南民族大学学报（自然科学版） 2025年第1期44卷 50-57页

作者：熊承义陈文旗高志荣马帅李帆中南民族大学电子信息工程学院武汉430074 中南民族大学智能无线通信湖北省重点实验室武汉430074 中南民族大学计算机科学学院武汉430074

研究了一种基于多头自注意力与卷积特征融合的磁共振图像Transformer重构方法.采用U型网络结构,通过学习图像的多尺度特征以提升重构性能.采用深度分离卷积与多头自注意力融合的Swin Transformer结构,改善网络的特征学习能力.在CC359-Br... 详细信息

研究了一种基于多头自注意力与卷积特征融合的磁共振图像Transformer重构方法.采用U型网络结构,通过学习图像的多尺度特征以提升重构性能.采用深度分离卷积与多头自注意力融合的Swin Transformer结构,改善网络的特征学习能力.在CC359-Brain数据集下基于多种采样模式进行仿真实验,结果证明了该方法在提升磁共振图像重构质量与降低系统复杂度方面的有效性.

关键词：磁共振成像卷积神经网络变换器深度学习

A Robust Face Recognition Method Using Multiple Features Fusion and Linear Regression

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Wuhan University Journal of Natural Sciences 2014年第4期19卷 323-327页

作者： GAO Zhirong DING Lixin xiong chengyi HUANG Bo School of Computer Wuhan University College of Computer Science South-Central University for Nationalities College of Electronics and Information South-Central University for Nationalities Shenzhen Institute of Wuhan University

This paper presents a robust face recognition algorithm by using transform domain-based multiple feature fusion and lin- ear regression. Transform domain-based feature fusion can provide comprehensive face information for recognition, and decrease the effect of variations in illumination and pose. The holistic feature and local feature are extracted by discrete cosine transform and Gabor wavelet transform, respectively. Then the extracted holistic features and the local features are fused by weighted sum. The fused feature values are finally sent to linear regression classifier for recognition. The algorithm is evaluated on AR, ORL and Yale B face databases. Experiment results show that our proposed algo- rithm could be more robust than those single feature-based algo- rithms under pose and expression variations.

关键词： holistic feature local feature weighted fusion

A Parallel-based Lifting Algorithm and VLSI Architecture for DWT

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Journal of Electronics(China) 2006年第2期23卷 244-248页

作者： xiong chengyi Tian Jinwen Liu Jian Gao Zhirong The State Key Lab of Education Commission for Image Processing and Intelligent Control Institute of Pattern Recognition ＆ Artificial Intelligence Huazhong Univ. of Science ＆ Tech. Wuhan 430074 China College of Electronic Info. Eng. South- Center Univ. for Nationalities Wuhan 430074 China Dept of Computer Science Wuhan Univ. of Science ＆ Eng. Wuhan 430074 China

A novel Parallel-Based Lifting Algorithm （PBLA） for Discrete Wavelet Transform （DWT）, exploiting the parallelism of arithmetic operations in all lifting steps, is proposed in this paper. It leads to reduce the critical path latency of computation, and to reduce the complexity of hardware implementation as well. The detailed derivation on the proposed algorithm, as well as the resulting Very Large Scale Integration （VLSI） architecture, is introduced, taking the 9/7 DWT as an example but without loss of generality. In comparison with the Conventional Lifting Algorithm Based Implementation （CLABI）, the critical path latency of the proposed architecture is reduced by more than half from （4Tm ＋ 8Ta）to Tm ＋ 4Ta, and is competitive to that of Convolution-Based Implementation （CBI）, but the new implementation will save significantly in hardware. The experimental results demonstrate that the proposed architecture has good performance in both increasing working frequency and reducing area.

关键词： Discrete Wavelet Transform (DFT) Lifting scheme Parallel Very Large Scale Integration(VLSI)

Tetraphenylethylene-doped covalent organic frameworks as a highly efficient aggregation-induced electrochemiluminescence emitter for ultrasensitive miRNA-21 analysis

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Advanced Sensor and Energy Materials

Advanced Sensor and Energy Materials 2023年第2期2卷 19-26页

作者： Wen-Yi Shu Ruiqi Su Linli Yao Yao Xiao Miao-Miao Chen Wei Wen Shengfu Wang chengyi xiong Xiuhua Zhang Collaborative Innovation Center for Advanced Organic Chemical Materials Co-constructed by the Province and Ministry Ministry of Education Key Laboratory for the Synthesis and Application of Organic Functional MoleculesCollege of Chemistry and Chemical EngineeringHubei UniversityWuhan 430062China State Key Laboratory of Biocatalysis and Enzyme Engineering School of Life SciencesHubei UniversityWuhan 430062China

MicroRNAs(miRNAs)as a well-known kind of cancer marker are closely associated with the formation and metastasis of ***,a novel tetraphenylethylene(TPE)-doped covalent organic frameworks(TPE-COFs)with strong aggregation-induced electrochemiluminescence(AIECL)response was synthesized and introduced to construct an ultrasensitive biosensor for the detection of *** strong aggregation-induced emission(AIE)response was obtained because the molecular motion of TPE was restricted by COFs which had the porosity and highly ordered topological ***,the porous structure of COFs allowed TPE to react with electrochemiluminescence(ECL)coreactants more ***,COFs significantly improved the electron transport efficiency of the entire ECL *** of these endowed the TPE-COFs with superior AIECL ***,a TPE-COFs based ECL resonance energy transfer(ECL-RET)system was constructed for ultrasensitive miRNA-21 biosensing with differential signal *** proposed assays exhibited excellent sensitivity with a wide dynamic range from 10 aM to 1 pM and a low detection limit of 2.18 ***,these indicated that doping TPE in COFs was a creative way to develop functional COFs and provided an effective way for enhancing ***,this work boarded the application of AIECL in analytical chemistry.

关键词： Aggregation-induced electrochemiluminescence Covalent organic frameworks Resonance energy transfer MicroRNA-21 Biosensor

有效的模(2^(n)+1)乘算法及其VLSI设计

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信号处理 2006年第5期22卷 703-706页

作者：熊承义田金文柳健中南民族大学电子信息工程学院武汉430074 华中科技大学图像识别与人工智能研究所国家教育部图像处理与智能控制重点实验室武汉430074

模乘运算在剩余数值系统、数字信号处理系统及其它领域都具有广泛的应用，模乘法器的硬件实现具有重要的作用。提出了一种改进的模（2^n＋1）余数乘法器的算法及其硬件结构，其输入为通常的二进制表示，因此无需另外的输入数据转换电路... 详细信息

模乘运算在剩余数值系统、数字信号处理系统及其它领域都具有广泛的应用，模乘法器的硬件实现具有重要的作用。提出了一种改进的模（2^n＋1）余数乘法器的算法及其硬件结构，其输入为通常的二进制表示，因此无需另外的输入数据转换电路而可直接用于数字信号处理应用。通过利用模（2^n＋1）运算的周期性简化其乘积项并重组求和项，以及采用改进的进位存储加法器和超前进位加法器优化结构以减少路径延时和硬件复杂度。比较其它同类设计，新的结构具有较好的面积、延时性能。

关键词：剩余数值系统模(2^n+1)乘法器周期性

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一种新的有效的小波变换VLSI结构

计算机工程 2005年第12期31卷 29-30,35页

作者：熊承义田金文柳健郑胜侯建华华中科技大学图像识别与人工智能研究所图像信息处理与智能控制教育部重点实验室中南民族大学电子与信息学院武汉430074

基于提升的小波变换算法,提出了一种新的功率面积有效的5-3和9-7小波变换的VLSI实现结构。采用时分复用和嵌入式并行流水线技术优化设计结构,有效地减少了所用乘法器、加法器运算单元和寄存器单元数量,以及对存储器的访问次数,从而有效... 详细信息

基于提升的小波变换算法,提出了一种新的功率面积有效的5-3和9-7小波变换的VLSI实现结构。采用时分复用和嵌入式并行流水线技术优化设计结构,有效地减少了所用乘法器、加法器运算单元和寄存器单元数量,以及对存储器的访问次数,从而有效地减少系统占用面积和功耗。系统实现了每一个时钟产生一个输出,输入信号的细节分量和近似分量交替输出。该结构具有简单、规则,以及扩展性好的特点,非常适合于VLSI设计实现。

关键词：提升小波变换时分复用技术嵌入式流水线技术 VLSI