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Application of optical proximity correction technology

Science in China(Series F) 2008年第2期51卷 213-224页

作者： cai yici ZHOU Qiang HONG XianLong SHI Rui WANG Yang Department of Computer Science and Technology Tsinghua University Beijing 100084 China

As process technology scales down to very deep sub-micron （VDSM） in semiconductor manufacturing technology, intrinsic size becomes close to or even shorter than the wavelength used for optical lithography. Thus, some distortions and deformations are introduced by optical proximity effects （OPE） mainly caused by the diffraction and interference of exposure light when layout patterns on a mask are transcribed to a wafer, which influence on the yield and performance of IC circuit. In order to compensate for the deformations, optical proximity correction （OPC） is the most commonly used methodology. Presently, the OPC method is to use a unitary toleration on the whole chip layer, which makes the run time of OPC algorithm longer, causes the size of GDSII files to follow exponential growth, and results in the cost of making mask grow immensely. Firstly, this paper proposes a selfadaptation OPC method with preprocessing function of patterns classification. According to the need of the correction precision, the OPC system divides patterns corrected into two groups with different toleration： critical patterns and general patterns, which enhance the efficiency of the OPC approach. Secondly, a model-based OPC method is presented based on pattern subsection and classifi- cation, which keeps the precision of the correction as well as enhances the efficiency. We also propose a rule-based OPC method with general, concise and complete correction rules, and achieve automatic-built rules-based and its looking-up. Thirdly, we also implement an OPC system, called MR-OPC; the MR-OPC system integrates both rule-based OPC and model-based OPC into a whole, so it can solve the confliction between the efficiency and precision. Experimental results show that the MR-OPC system we suggested has advantages of the efficiency and expansibility.

关键词： OPC rules-based model-based layout IC

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A single layer zero skew clock routing in X architecture

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Science in China(Series F) 2009年第8期52卷 1466-1475页

作者： SHEN WeiXiang cai yici HONG XianLong HU Jiang LU Bing Electronic Design Automation Laboratory Departmeat of Computer Science and Technology Tsinghua University Beijing 100084 China Electrical and Computer Engineering Texas A&M University College Station TX 77843 USA Cadence Design Systems Inc 35 Spring Street New Providence NJ 07974 USA

With its advantages in wirelength reduction and routing flexibility compared with conventional Manhattan routing, X architecture has been proposed and applied to modern IC design. As a critical part in high-performance integrated circuits, clock network design meets great challenges due to feature size decrease and clock frequency increase. In order to eliminate the delay and attenuation of clock signal introduced by the vias, and to make it more tolerant to process variations, in this paper, we propose an algorithm of a single layer zero skew clock routing in X architecture （called Pianar-CRX）. Our Planar- CRX method integrates the extended deferred-merge embedding algorithm （DME-X, which extends the DME algorithm to X architecture） with modified Ohtsuki＇s line-search algorithm to minimize the total wirelength and the bends. Compared with planar clock routing in the Manhattan plane, our method achieves a reduction of 6.81% in total wirelength on average and gets the resultant clock tree with fewer bends. Experimental results also indicate that our solution can be comparable with previous non-planar zero skew clock routing algorithm.

关键词： clock routing single layer X architecture zero skew

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Minimum Error Based Affine Arithmetic for Variational Timing Analysis

Minimum Error Based Affine Arithmetic for Variational Timing...

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2005 6th International Conference on ASIC

作者： Yi Zou Mengsheng Zhang yici cai Qiang Zhou Xianlong Hong Department of Computer Science and Technology Tsinghua University

ISBN: (纸本)0780392108;9780780392106

＜正＞In this paper,we describes a novel improvement for affine arithmetic which is widely used in statistical timing analysis and circuit *** representation and calculation method for affine arithmetic is both simple and accurate comparing with previous *** rule for calculating interval multiplication is simple and *** can both give a conservative bound and a minimum error affine approximation at the same *** application for variational timing analysis demonstrated the usefulness of affine arithmetic.

关键词： Timing Circuit simulation Circuit analysis Upper bound Analytical models Computer errors Computer science Digital arithmetic Sensitivity analysis Convergence

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Time-domain analysis methodology for large-scale RLC circuits and its applications

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Science in China(Series F) 2006年第5期49卷 665-680页

作者： LUO Zuying cai yici Sheldon X.-D Tan HONG Xianlong WANG Xiaoyi PAN Zhu FU Jingjing Department of Computer Science and Technology Tsinghua University Beijing 100084 China College of Information Science and Technology Beijing Normal University Beijing 100875 China Department of Electrical Engineering University of California at Riverside Riverside CA92521 USA

With soaring work frequency and decreasing feature sizes, VLSI circuits with RLC parasitic components are more like analog circuits and should be carefully analyzed in physical design. However, the number of extracted RLC components is typically too large to be analyzed efficiently by using present analog circuit simulators like SPICE. In order to speedup the simulations without error penalty, this paper proposes a novel methodology to compress the time-descritized circuits resulted from numerical integration approximation at every time step. The main contribution of the methodology is the efficient structure-level compression of DC circuits containing many current sources, which is an important complement to present circuit analysis theory. The methodology consists of the following parts： 1） An approach is proposed to delete all intermediate nodes of RL branches. 2） An efficient approach is proposed to compress and back-solve parallel and serial branches so that it is error-free and of linear complexity to analyze circuits of tree topology. 3） The Y to πtransformation method is used to error-free reduce and back-solve the intermediate nodes of ladder circuits with the linear complexity. Thus, the whole simulation method is very accurate and of linear complexity to analyze circuits of chain topology. Based on the methodology, we propose several novel algorithms for efficiently solving RLC-model transient power/ground （P/G） networks. Among them, EQU-ADI algorithm of linear-complexity is proposed to solve RLC P/G networks with mesh-tree or mesh-chain topologies. Experimental results show that the proposed method is at least two orders of magnitude faster than SPICE while it can scale linearly in both time- and memory-complexity to solve very large P/G networks.

关键词： RLC circuits analog circuit analysis time-domain analysis PIG networks algorithm complexity

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Accelerating PCG power/ground network solver on GPGPU

Accelerating PCG power/ground network solver on GPGPU

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2009 IEEE 8th International Conference on ASIC(ASICON 2009)

作者： yici cai and Jin Shi

Currently fast and precise P/G （power/ground） solvers are critical for robust P/G designs,but traditional serial P/G solvers are somewhat incapable of millions of nodes in P/*** spite of powerful computation capability of parallel hardware,paralleled P/G solvers are far from prevailing,especially on complicated special *** anticipated it,and studied on parallelizing and accelerating P/G solvers on *** our work,we developed a PCG（Preconditioned Conjugate Gradient）-based P/G solver on the CUDA platform for structured P/G network,and identified advantages as well as constraints from GPU *** PCG-GPU solver can be up to 40 times faster than SuperLU,and also outperform multi-grid based solver on GPU.

关键词： P/G simulation PCG GPGPU

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Progress and Research on Interconnects Crosstalk in Deep Submicron Technology

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Journal of Semiconductors 2003年第11期24卷 1121-1129页

作者：蔡懿慈赵鑫洪先龙清华大学计算机科学与技术系北京100084

As develops in deep sub micron designs,the interconnect crosstalk becomes much more *** cially, the coupling inductance can not be ignored in gigahertz *** shield insertion is an efficient technique to reduce the inductive *** this paper,the characteristics of on chip mutual inductance (as well as self) for coplanar,micro stripline and stripline structures are introduced *** base on the coplanar interconnect structures,the effective coupling K eff model and the RLC explicit noise model are proposed *** results of experiments show that these two models both have high fidelity.

关键词： interconnect crosstalk crosstalk noise K eff model RLC explicit noise model

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Detailed Routing Algorithm with Optical Proximity Effects Constraint

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Journal of Semiconductors 2007年第2期28卷 189-195页

作者：周强蔡懿慈张为洪先龙清华大学计算机科学与技术系北京100084

We present a detailed routing algorithm considering the optical proximity effect. The light intensity is calculated beforehand and stored in look-up tables. These costs are used as a constraint to guide the sequential routing. The routing algorithm is based on constructed force directed Steiner tree routing to enhance routing efficien- cy. Experimental results on industrial benchmark circuits show that the presented routing algorithm can obtain much improvement considering optical effects short runtime.

关键词： optical proximity effect detailed routing Steiner tree yield

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通过电源完整性分析和电迁移修复提高供电网络可靠性

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计算机辅助设计与图形学学报 2022年第4期34卷 499-506页

作者：王晶蔡懿慈周强清华大学计算机科学与技术系北京100084

电迁移是集成电路供电网络的关键失效因素,由于芯片集成度和电流密度的增加,供电网络设计留给电迁移优化的余量越来越小.供电网络的传统设计缺乏电迁移和电压降的综合分析,会造成设计的过度约束.为避免上述问题,提出一种基于通孔灵敏度... 详细信息

电迁移是集成电路供电网络的关键失效因素,由于芯片集成度和电流密度的增加,供电网络设计留给电迁移优化的余量越来越小.供电网络的传统设计缺乏电迁移和电压降的综合分析,会造成设计的过度约束.为避免上述问题,提出一种基于通孔灵敏度分析的供电网络优化方法.首先,通过伴随矩阵的方法验证通孔的灵敏度对电迁移和电压降的影响;然后,结合供电网络的结构,针对关键通孔制定梯度优化策略,避免电迁移过度优化;最后,采用配置通孔阵列结构的方法提高通孔的可靠性.所提分析方法基于32核服务器实现,并通过IBM benchmark进行验证.实验结果表明,与全通孔优化的策略比较,所提方法以极小的面积代价实现电迁移优化,并且协同优化后,电路不存在电压降违规.

关键词：电迁移优化可靠性通孔阵列供电网络

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随机行走算法研究及其在电源/地线网络瞬态优化中的应用

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计算机辅助设计与图形学学报 2007年第9期19卷 1178-1183页

作者：康乐蔡懿慈洪先龙清华大学计算机科学与技术系北京100084

实验分析了电源/地线(P/G)网络的随机行走算法,与传统的预优共轭梯度法比较发现,当随机行走求解较少节点时性能较好,但在大规模P/G网络瞬态分析中相对较慢.通过修改随机行走过程进行伴随网络的瞬态分析,提出一种快速计算灵敏度的算法.... 详细信息

实验分析了电源/地线(P/G)网络的随机行走算法,与传统的预优共轭梯度法比较发现,当随机行走求解较少节点时性能较好,但在大规模P/G网络瞬态分析中相对较慢.通过修改随机行走过程进行伴随网络的瞬态分析,提出一种快速计算灵敏度的算法.实验结果表明,该算法计算时间较短,与精确结果误差较小.

关键词：电源/地线网络随机行走速度与精度瞬态分析灵敏度

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物理设计EDA中可扩展数据支撑系统结构

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计算机辅助设计与图形学学报 2005年第7期17卷 1395-1400页

作者：周强蔡琪洪先龙蔡懿慈清华大学计算机科学与技术系北京100084 中国航空结算中心北京100028

提出了一种可扩展的数据支撑系统结构,该系统为EDA物理设计工具开发提供数据支持·当设计工艺技术进入超深亚微米后,物理设计过程复杂性增加,大数据量、复杂结构的数据表示成为一个关键问题·需要提供一个有效的、可扩展的数据支撑环境... 详细信息

提出了一种可扩展的数据支撑系统结构,该系统为EDA物理设计工具开发提供数据支持·当设计工艺技术进入超深亚微米后,物理设计过程复杂性增加,大数据量、复杂结构的数据表示成为一个关键问题·需要提供一个有效的、可扩展的数据支撑环境,支持多层次、多迭代、结构化设计过程的集成·该数据支撑系统采用可扩展标记语言XML表示设计数据,完成设计过程大规模、多种类、多阶段数据表示和处理,提高数据系统的可扩展性·文中对该数据支撑系统结构进行了说明,结合实际集成需求,对数据表示、数据解析和数据转换等关键技术的处理也进行了详细说明·

关键词： EDA 数据支撑系统软件系统结构

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