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Journal of Semiconductors 2012年第1期33卷 144-148页

作者： Tong Xingyuan zhu zhangming yang yintang School of Electronic Engineering Xi'an University of Posts&Telecommunications Xi'an 710121China institute of microelectronics Xidian University Xi'an 710071China

An offset cancellation technique for a SAR （successive approximation register） ADC switched-capacitor comparator is described. The comparator is designed with a pre-amplifying and regenerative latching structure and realized in 0.18μm CMOS. With the first stage preamplifier offset cancellation and low offset regenerative latching approach, the equivalent offset of the comparator is reduced to 〈 0.55 mV. By using the pre-amplifying and regenerative latching comparison mode the comparator exhibits low power dissipation. Under a 1.8 V power supply, with a 200 kS/s ADC sampling rate and 3 MHz clock frequency, a 13-bit comparison resolution is reached and less than 0.09 mW power dissipation is consumed. The superiority of this comparator is discussed and proved by the post-simulation and application to a 10 bit 200 kS/s touch screen SAR A/D converter.

关键词： A/D converter switched-capacitor comparator preamplifier regenerative latch low power low off-set

A congestion-aware OE router employing fair arbitration for network-on-chip

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Journal of Semiconductors 2018年第12期39卷 190-196页

作者： Lu Liu Yadong Sun zhangming zhu yintang yang School of microelectronics Xidian University

To meet the demand for high on-chip network performance, flexible routing algorithms supplying path diversity and congestion alleviation are required. We propose a CAOE-FA router as a combination of congestionawareness and fair arbitration. Buffer occupancies from downstream neighbors are collected to indicate the congestion levels, among the candidate outputs permitted by the odd-even(OE) turn model, the lightest loaded direction is selected; fair arbitration is employed for the condition of the same congestion level to replace random selection. Experimental results show that the CAOE-FA can reduce the average packet latency by up to 22.18% and improve the network throughput by up to 68.58%, with ignorable price of hardware cost.

关键词： network-on-chip odd-even turn model congestion-aware router fair arbitration

SHA-less architecture with enhanced accuracy for pipelined ADC

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Journal of Semiconductors 2012年第2期33卷 117-121页

作者： Zhao Lei yang yintang zhu zhangming Liu Lianxi School of microelectronics Xidian UniversityXi’an 710071China

A new design technique for merging the front-end sample-and-hold amplifier（SHA） into the first multiplying digital-to-analog converter（MDAC） is *** reducing the aperture error in the first stage of the pipelined ADC,a symmetrical structure is used in a flash ADC and ***,a variable resistor tuning network is placed at the flash input to compensate for different cutoff frequencies of the input impedances of the flash and *** circuit also has a clear clock phase in the MDAC and separate sampling capacitors in the flash ADC to eliminate the nonlinear charge kickback to the input *** proposed circuit,designed using ASMC 0.35-μm BiCMOS technology,occupies an area of 1.4 x 9 mm^2 and is used as the front-end stage in a 14-bit 125-MS/s pipelined *** the trim circuit is enabled,the measured signal-to-noise ratio is improved from 71.5 to 73.6 dB and the spurious free dynamic range is improved from 80.5 to 83.1 dB with a 30.8 MHz input. The maximum input frequency is up to 150 MHz without steep performance degradations.

关键词： pipelined analog-to-digital converter sample-and-hold amplifier SHA-less aperture error

A self-powered piezoelectric energy harvesting interface circuit with efficiency- enhanced P-SSHI rectifier

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Journal of Semiconductors 2018年第4期39卷 55-65页

作者： Lianxi Liu Yanbo Pang Wenzhi Yuan zhangming zhu yintang yang School of microelectronics Xidian University Xi'an 710071 China Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices Xi'an 710071 China

The key to self-powered technique is initiative to harvest energy from the surrounding environment. Harvesting energy from an ambient vibration source utilizing piezoelectrics emerged as a popular method. Effi- cient interface circuits become the main limitations of existing energy harvesting techniques. In this paper, an inter- face circuit for piezoelectric energy harvesting is presented. An active full bridge rectifier is adopted to improve the power efficiency by reducing the conduction loss on the rectifying path. A parallel synchronized switch harvesting on inductor （P-SSHI） technique is used to improve the power extraction capability from piezoelectric harvester, thereby trying to reach the theoretical maximum output power. An intermittent power management unit （IPMU） and an output capacitor-less low drop regulator （LDO） are also introduced. Active diodes （AD） instead of tradition- al passive ones are used to reduce the voltage loss over the rectifier, which results in a good power efficiency. The IPMU with hysteresis comparator ensures the interface circuit has a large transient output power by limiting the output voltage ranges from 2.2 to 2 V. The design is fabricated in a SMIC 0.18/~m CMOS technology. Simulation results show that the flipping efficiency of the P-SSHI circuit is over 80% with an off-chip inductor value of 820/zH. The output power the proposed rectifier can obtain is 44.4/~W, which is 6.7x improvement compared to the maximum output power of a traditional rectifier. Both the active diodes and the P-SSHI help to improve the output power of the proposed rectifier. LDO outputs a voltage of 1.8 V with the maximum 90% power efficiency. The proposed P-SSHI rectifier interface circuit can be self-powered without the need for additional power supply.

关键词： self-powered piezoelectric energy harvesting P-SSHI power management active diode LDO

Modeling and Measurement of 3D Solenoid Inductor Based on Through-Silicon Vias

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Chinese Journal of Electronics 2023年第2期32卷 365-374页

作者： YIN Xiangkun WANG Fengjuan zhu zhangming Vasilis F.Pavlidis LIU Xiaoxian LU Qijun LIU yang yang yintang Shaanxi Key Lab.of Integrated Circuits and Systems School of Microelectronics Xidian University School of Automation and Information Engineering Xi'an University of Technique Department of Computer Science University of Manchester

Through-silicon via(TSV) provides vertical interconnectivity among the stacked dies in three-dimensional integrated circuits(3D ICs) and is a promising option to minimize 3D solenoid inductors for on-chip radio-frequency applications. In this paper, a rigorous analytical inductance model of 3D solenoid inductor is proposed based on the concept of loop and partial inductance. And a series of 3D samples are fabricated on 12-in high-resistivity silicon wafer using low-cost standard CMOS-compatible process. The results of the proposed model match very well with those obtained by simulation and measurement. With this model, the inductance can be estimated accurately and efficiently over a wide range of inductor windings, TSV height, space, and pitch.

关键词： Semiconductor device modeling Inductance Analytical models Solid modeling Three-dimensional displays Integrated circuit modeling Inductors

A high efficiency PWM CMOS class-D audio power amplifier

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Journal of Semiconductors 2009年第2期30卷 48-53页

作者：朱樟明刘帘曦杨银堂雷晗 institute of microelectronics Xidian University Xi'an Power-Rail Micro Co. Ltd

Based on the difference close-loop feedback technique and the difference pre-amp, a high efficiency PWM CMOS class-D audio power amplifier is proposed. A rail-to-rail PWM comparator with window function has been embedded in the class-D audio power amplifier. Design results based on the CSMC 0.5μm CMOS process show that the max efficiency is 90%, the PSRR is -75 dB, the power supply voltage range is 2.5-5.5 V, the THD＋N in 1 kHz input frequency is less than 0.20%, the quiescent current in no load is 2.8 mA, and the shutdown current is 0.5 pA, The active area of the class-D audio power amplifier is about 1.47 × 1.52 mm^2. With the good performance, the class-D audio power amplifier can be applied to several audio power systems.

关键词： class-D audio amplifier PWM CMOS high efficiency rail-to-rail comparator difference

Stacked arrangement of substrate integrated waveguide cavity-backed semicircle patches for wideband circular polarization with filtering effect

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Frontiers of Information Technology & Electronic Engineering 2023年第5期24卷 759-766页

作者： Yitong YAO Gang DONG zhangming zhu yintang yang School of microelectronics Xidian UniversityXi’an 710071China

We present a novel broadband circularly polarized(CP)antenna with filtering effect for X-and Kuband satellite wireless *** structure comprises a driven layer(also a filtering layer)and a stacked layer(also a CP layer).The bandpass filtering response consists of two radiation nulls,which is the combined effect of a substrate integrated waveguide(SIW)cavity-backed aperture and embedded driven patch.

关键词： waveguide polarization antenna

A high EMS daisy-chain SPI interface for battery monitor system

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Journal of Semiconductors 2017年第3期38卷 120-124页

作者： Qidong Zhang yintang yang Changchun Chai institute of microelectronics Xidian University Xi'an 710071 China

A high EMS current-mode SPI interface for battery monitor IC（BMIC） is presented to form a daisychain bus configuration for the cascaded BMICs and the communication between the MCU and master *** on analog and digital mixed filtering technique,the proposed daisy-chain can avoid the isolated communication issue in electromagnetic interference environment,and reduce the extensively required I/O ports of MCU,at the same time reduce the system *** proposed daisy-chain interface was introduced in a 6-ch battery monitor IC which was fabricated with 0.35μ m 30 V BCD *** measurement result shows that the presented daisy-chain SPI interface achieves better EMS performance with different EMI injection while just consuming a total operation current up to 1 m A.

关键词： SPI daisy-chain EMS EMI battery monitor battery management

Effect of dummy vias on interconnect temperature variation

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Chinese Science Bulletin 2011年第21期56卷 2286-2290页

作者： WANG Zeng DONG Gang yang yintang LI JianWei Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices Microelectronics InstituteXidian UniversityXi'an 710071China

The number of the dummy via can significantly affect the interconnect average *** paper explores the modeling of the interconnect average temperature in the presence of multiple dummy *** proposed model incorporates the multi-via effect into the effective thermal conductivity of the interlayer dielectric (ILD) to obtain accurate *** different ILDs,the multi-via effect is analyzed and ***,the extended applications of the multi-via effect are presented in this paper to obtain the minimum interconnect average temperature increase with a given via separation or *** study suggests that the multi-via effect should be accounted for in integrated circuits design to optimize the performance and design accuracy of integrated circuits.

关键词：互连温度变化集成电路设计平均温度平均气温层间绝缘优化设计 ILD