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Towards dataflow based graph processing

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Science China(Information Sciences) 2017年第12期60卷 274-276页

作者： Hai JIN Pengcheng YAO xiaofei liao Service Computing Technology and System Lab Cluster and Grid Computing Lab Big Data Technology and System Lab School of Computer Science and Technology Huazhong University of Science and Technology

Modern graph processing is widely used for solving a vast variety of real-world problems,e.g.,web sites ranking[1]and community detection[2].To better adapt and express the procedure of graph iteration,a wide spectrum... 详细信息

关键词： ILP cycle Towards dataflow based graph processing

An E-band CMOS frequency quadrupler with 1.7-dBm output power and 45-dB fundamental suppression

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Journal of Semiconductors 2022年第9期43卷 46-52页

作者： xiaofei liao Dixian Zhao Xiaohu You National Mobile Communication Research Laboratory Southeast UniversityNanjing 211189China Purple Mountain Laboratories Nanjing 211111China

This paper presents an E-band frequency quadrupler in 40-nm CMOS *** circuit employs two push-push frequency doublers and two single-stage neutralized *** pseudo-differential class-B biased cascode topo-logy is adopted for the frequency doubler,which improves the reverse isolation and the conversion *** tech-nique is applied to increase the stability and the power gain of the amplifiers *** stacked transformers are used for single-ended-to-differential transformation as well as output bandpass *** output bandpass filter enhances the 4th-harmonic output power,while rejecting the undesired harmonics,especially the 2nd *** core chip is 0.23 mm^(2)in size and consumes 34 *** measured 4th harmonic achieves a maximum output power of 1.7 dBm with a peak conversion gain of 3.4 dB at 76 *** fundamental and 2nd-harmonic suppressions of over 45 and 20 dB are achieved for the spectrum from 74 to 82 GHz,respectively.

关键词： capacitor neutralization CMOS E-band frequency doubler frequency quadrupler push-push

UCat: heterogeneous memory management for unikernels

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Frontiers of Computer Science 2023年第1期17卷 51-61页

作者： Chong TIAN Haikun LIU xiaofei liao Hai JIN National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab/Cluster and Grid Computing LabSchool of Computing Science and TechnologyHuazhong University of Science and TechnologyWuhan 430074China

Unikernels provide an efficient and lightweight way to deploy cloud computing services in application-specialized and single-address-space virtual machines (VMs). They can efficiently deploy hundreds of unikernel-based VMs in a single physical server. In such a cloud computing platform, main memory is the primary bottleneck resource for high-density application deployment. Recently, non-volatile memory (NVM) technologies has become increasingly popular in cloud data centers because they can offer extremely large memory capacity at a low expense. However, there still remain many challenges to utilize NVMs for unikernel-based VMs, such as the difficulty of heterogeneous memory allocation and high performance overhead of address *** this paper, we present UCat, a heterogeneous memory management mechanism that support multi-grained memory allocation for unikernels. We propose front-end/back-end cooperative address space mapping to expose the host memory heterogeneity to unikernels. UCat exploits large pages to reduce the cost of two-layer address translation in virtualization environments, and leverages slab allocation to reduce memory waste due to internal memory fragmentation. We implement UCat based on a popular unikernel--OSv and conduct extensive experiments to evaluate its efficiency. Experimental results show that UCat can reduce the memory consumption of unikernels by 50% and TLB miss rate by 41%, and improve the throughput of real-world benchmarks such as memslap and YCSB by up to 18.5% and 14.8%, respectively.

关键词： unikernel virtualization non-volatile memory heterogeneous memory large page slab allocation

Resource abstraction and data placement for distributed hybrid memory pool

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Frontiers of Computer Science 2021年第3期15卷 47-57页

作者： Tingting CHEN Haikun LIU xiaofei liao Hai JIN National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab/Gluster and Grid Computing LabSchool of Gomputing Science and TechnologyHuazhong University of Science and TechnologyWuhan 430074China

Emerging byte-addressable non-volatile memory(NVM)technologies offer higher density and lower cost than DRAM,at the expense of lower performance and limited write *** have been many studies on hybrid NVM/DRAM memory management in a single physical ***,it is still an open problem on how to manage hybrid memories efficiently in a distributed *** paper proposes Alloy,a memory resource abstraction and data placement strategy for an RDMA-enabled distributed hybrid memory pool(DHMP).Alloy provides simple APIs for applications to utilize DRAM or NVM resource in the DHMP,without being aware of the hardware details of the *** propose a hotness-aware data placement scheme,which combines hot data migration,data replication and write merging together to improve application performance and reduce the cost of *** evaluate Alloy with several micro-benchmark workloads and public benchmark *** results show that Alloy can significantly reduce the DRAM usage in the DHMP by up to 95%,while reducing the total memory access time by up to 57%compared with the state-of-the-art approaches.

关键词： load balance distributed hybrid memory clouds

ReCSA:a dedicated sort accelerator using ReRAM-based content addressable memory

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Frontiers of Computer Science 2023年第2期17卷 1-13页

作者： Huize LI Hai JIN Long ZHENG Yu HUANG xiaofei liao National Engineering Research Center for Big Data Technology and System Services Computing Technology and System LabClusters and Grid Computing LabSchool of Computer Science and TechnologyHuazhong University of Science and TechnologyWuhan 430074China

With the increasing amount of data,there is an urgent need for efficient sorting algorithms to process large data *** sorting algorithms have attracted much attention because they can take advantage of different hardware's *** the traditional hardware sort accelerators suffer“memory wall”problems since their multiple rounds of data transmission between the memory and the *** this paper,we utilize the in-situ processing ability of the ReRAM crossbar to design a new ReCAM array that can process the matrix-vector multiplication operation and the vector-scalar comparison in the same array *** this designed ReCAM array,we present ReCSA,which is the first dedicated ReCAM-based sort *** hardware designs,we also develop algorithms to maximize memory utilization and minimize memory exchanges to improve sorting *** sorting algorithm in ReCSA can process various data types,such as integer,float,double,and *** also present experiments to evaluate the performance and energy efficiency against the state-of-the-art sort *** experimental results show that ReCSA has 90.92×,46.13×,27.38×,84.57×,and 3.36×speedups against CPU-,GPU-,FPGA-,NDP-,and PIM-based platforms when processing numeric data *** also has 24.82×,32.94×,and 18.22×performance improvement when processing string data sets compared with CPU-,GPU-,and FPGA-based platforms.

关键词： ReCAM parallel sorting architecture design processing-in-memory

A hybrid memory architecture supporting fine-grained data migration

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Frontiers of Computer Science 2024年第2期18卷 31-41页

作者： Ye CHI Jianhui YUE xiaofei liao Haikun LIU Hai JIN National Engineering Research Center for Big Data Technology and System Services Computing Technology and System LabCluster and Grid Computing LabSchool of Computer Science and TechnologyHuazhong University of Science and TechnologyWuhan 430074China Department of Computer Science Michigan Technological UniversityMichigan 49931USA

Hybrid memory systems composed of dynamic random access memory(DRAM)and Non-volatile memory(NVM)often exploit page migration technologies to fully take the advantages of different memory *** previous proposals usually migrate data at a granularity of 4 KB pages,and thus waste memory bandwidth and DRAM *** this paper,we propose Mocha,a non-hierarchical architecture that organizes DRAM and NVM in a flat address space physically,but manages them in a cache/memory *** the commercial NVM device-Intel Optane DC Persistent Memory Modules(DCPMM)actually access the physical media at a granularity of 256 bytes(an Optane block),we manage the DRAM cache at the 256-byte size to adapt to this feature of *** design not only enables fine-grained data migration and management for the DRAM cache,but also avoids write amplification for Intel Optane *** also create an Indirect Address Cache(IAC)in Hybrid Memory Controller(HMC)and propose a reverse address mapping table in the DRAM to speed up address translation and cache ***,we exploit a utility-based caching mechanism to filter cold blocks in the NVM,and further improve the efficiency of the DRAM *** implement Mocha in an architectural *** results show that Mocha can improve application performance by 8.2%on average(up to 24.6%),reduce 6.9%energy consumption and 25.9%data migration traffic on average,compared with a typical hybrid memory architecture-HSCC.

关键词： non-volatile memory hybrid memory system data migration fine-grained caching

Understanding and identifying latent data races cross-thread interleaving

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Frontiers of Computer Science 2015年第4期9卷 524-539页

作者： Long ZHEN~ xiaofei liao Song WU Xuepeng FAN Hai JIN Services Computing Technology and System Laboratory Cluster and Grid Computing Laboratory School of Computer Science and Technology Huazhong University of Science and Technology Wuhan 430074 China

Data races are ubiquitous in multi-threaded ap- plications, but they are by no means easy to detect. One of the most important reasons is the complexity of thread in- terleavings. A volume of research has been devoted to the interleaving-insensitive detection. However, all the previous work focuses on the uniform detection （unknown to the char- acteristics of thread interleavings）, thereby making the detec- tion defective in either reporting false positives or suffering from prohibitive overhead. To cope with the problem above, we propose an efficient, precise, and sound step-by-step res- olution based on the characteristics of thread interleavings. We first try to tease apart the categories of thread interleav- ings from the several typical sources arising from the lock synchronizations. We then conduct a brief study and find a new and complex pattern the previous work cannot detect. It is also revealed that the simple pattern with the majority of thread interleavings can be resolved by a simple processing to achieve a big profit for the previous reordering-based design. Our final experimental results demonstrate the effectiveness of our empiricism-based approach, and show that 51.0% of execution time and 52.3 % of trace size arising from the state- of-the-art reordering technique can be saved through a quick filtering of the simple pattern with a negligible （4.45%） per- formance overhead introduced on-the-fly.

关键词： data race happens-before thread interleaving

Writeback throttling in a virtualized system with SCM

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Frontiers of Computer Science 2016年第1期10卷 82-95页

作者： Dingding LI xiaofei liao Hai JIN Yong TANG Gansen ZHAO School of Computer Science South China Normal University Guangzhou 510631 China School of Computer Science and Technology Huazhong University of Science and Technology Wuhan 430074 China

Storage class memory （SCM） has the potential to revolutionize the memory landscape by its non-volatile and byte-addressable properties. However, there is little published work about exploring its usage for modem virtualized cloud infrastructure. We propose SCM-vWrite, a novel architecture designed around SCM, to ease the performance interference of virtualized storage subsystem. Through a case study on a typical virtualized cloud system, we first describe why cur- rent writeback manners are not suitable for a virtualized en- vironment, then design and implement SCM-vWrite to im- prove this problem. We also use typical benchmarks and re- alistic workloads to evaluate its performance. Compared with the traditional method on a conventional architecture, the ex- perimental result shows that SCM-vWrite can coordinate the writeback flows more effectively among multiple co-located guest operating systems, achieving a better disk I/O perfor- mance without any loss of reliability.

关键词： virtualization storage class memory writeback

An adaptive switching scheme for iterative computing in the cloud

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Frontiers of Computer Science 2014年第6期8卷 872-884页

作者： Yu ZHANG xiaofei liao Hai JIN Li LIN Feng LU Service Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan 430074 China

Delta-based accumulative iterative computation （DAIC） model is currently proposed to support iterative algorithms in a synchronous or an asynchronous way. However, both the synchronous DAIC model and the asynchronous DAIC model only satisfy some given conditions, respectively, and perform poorly under other conditions either for high synchronization cost or for many redundant activations. As a result, the whole performance of both DAIC models suffers from the serious network jitter and load jitter caused by multi- tenancy in the cloud. In this paper, we develop a system, namely Hyblter, to guarantee the performance of iterative algorithms under different conditions. Through an adaptive execution model selection scheme, it can efficiently switch between synchronous and asynchronous DAIC model in order to be adapted to different conditions, always getting the best performance in the cloud. Experimental results show that our approach can improve the performance of current solutions up to 39.0%.

关键词： iterative algorithm computational skew communication skew cloud delta-based accumulative iterative computation