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Cache Power Optimization Based on Compare-Based Adaptive Clock Gating and Its 65nm SoC Implementation

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Chinese Journal of Electronics 2017年第1期26卷 128-131页

作者： LI Jie WAN Xing WU Jianbing shan weiwei National ASIC System Engineering Research Center Southeast University

In most embedded microprocessor based System on chips(So Cs), cache has become a ma jor source of power consumption due to its increasing size and high access rate. Power optimization of cache based on Compare-based adaptive clock gating(CACG) is proposed to reduce the power waste due to cache idle. By detecting the cache's working state, the CACG can automatically turn off its clock when it is in idle state, saving a large percentage of dynamic power. Measurements of a real So C chip fabricated under TSMC 65 nm CMOS process show that an average of 30.3% power reduction is gained in Dhrystone test benchmark at a cost of negligible area overhead and no virtually performance loss.

关键词： Self-adaptive clock gating Embedded processor Cache idle Low power

Low Overhead and Fast Reaction Adaptive Clocking System for Voltage Droop Tolerance

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Chinese Journal of Electronics 2019年第3期28卷 503-507页

作者： shanG Xinchao shan weiwei XIANG Yiming WAN Liang FAN Ao National ASIC System Engineering Research Center Southeast University

Variation in on-chip power supply continues to be a major challenge to limit circuit performance. To mitigate the impact of high-frequency voltage droop, a novel all-digital adaptive clock system is proposed. The adaptive clock system is composed of a droop detector and an adaptive clock generator, which directly stretch the clock period when the circuit suffers from the supply voltage droop. The droop detector circuit detects the VDD droop and the digital adaptive clock generator circuit selects the stretched clock to prevent timing-margin failures. The response time for droop detection and clock stretch can be as fast as one cycle. The whole scheme is used on a test circuit under SMIC 40 nm CMOS process with a layout area of 900 um*1100 um. Postlayout simulation results demonstrate power reductions are 7% at 1.1 V and 15% at 0.7 V for a 10% VDD droop,respectively.

关键词： Voltage droop Adaptive clock system Droop detector Adaptive clock generator

An Ultra Low Steady-State Current Power-on-Reset Circuit in 65nm CMOS Technology

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Chinese Journal of Electronics 2014年第4期23卷 678-681页

作者： shan weiwei WANG Xuexiang LIU Xinning SUN Huafang National ASIC System Engineering Research Center Southeast University

A novel Power-on-reset(POR) circuit is proposed with ultra-low steady-state current consumption. A band-gap voltage comparator is used to generate a stable pull-up voltage. To eliminate the large current consumptions of the analog part, a power switch is adopted to cut the supply of band-gap voltage comparator, which gained ultra-low current consumption in steady-state after the POR rest process completed. The state of POR circuit is maintained through a state latch circuit. The whole circuit was designed and implemented in 65 nm CMOS technology with an active area of 120μm*160μm. Experimental results show that it has a steady pull-up voltage of 0.69 V and a brown-out voltage of 0.49 V under a 1.2V supply voltage rising from 0V, plus its steady-state current is only9 n A. The proposed circuit is suitable to be integrated in system on chip to provide a reliable POR signal.

关键词： Power-on-reset circuit Brown-out detection Ultra-low steady-state current Band-gap voltage comparator

Near-Threshold Wide-Voltage Design Review

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Tsinghua Science and Technology 2023年第4期28卷 696-718页

作者： Yan Zhao Jun Yang Chao Chen weiwei shan Peng Cao Yongliang Zhou Ziyu Li Tai Yang National Application Specific Integrated Circuit(ASIC)Center Southeast UniversityNanjing 210096China

This paper presents a comprehensive review of near-threshold wide-voltage designs on memory,resilient logic designs,low voltage Radio Frequency(RF)circuits,and timing *** the prosperous development of wearable applications,low power consumption has become one of the primary challenges for IC *** improve the power efficiency,the prefer scheme is to operate at an ultra low voltage of Near Threshold Voltage(NTV).For the performance variation and degradation,a self-adaptive margin assignment technique is proposed in the low *** proposed technique tracks the circuit states in real time and dynamically allocates voltage margins,reducing the minimum supply voltage and achieving higher energy *** self-adaptive margin assignment technique can be used in Static Random Access Memory(SRAM),digital circuits,and analog/RF *** on the self-adaptive margin assignment technique,the minimum voltage in the 40 nm CMOS process is reduced to 0.6 V or even lower,and the energy efficiency is increased by 3–4 times.

关键词： Near Threshold Voltage(NTV) wide-voltage memory resilient logic design low voltage Radio Frequency(RF) timing analysis

An Improved Path Delay Variability Model via Multi-Level Fan-Out-of-4 Metric for Wide-Voltage-Range Digital CMOS Circuits

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Chinese Journal of Electronics 2023年第2期32卷 375-388页

作者： CUI Yuqiang shan weiwei DAI Wentao LIU Xinning GUO Jingjing CAO Peng National ASIC System Engineering Research Center Southeast University Cadence Design Systems Inc. Nanjing University of Posts and Telecommunications

In advanced CMOS technology, process,voltage, and temperature(PVT) variations increase the paths’ latency in digital circuits, especially when operating at a low supply voltage. The fan-out-of-4 inverter chain(FO4 chain) metric has been proven to be a good metric to estimate the path’s delay variability, whereas the previous work ignored the non-independent characteristic between the adjacent cells in a path. In this study,an improved model of path delay variability is established to describe the relationship between the paths’ max-delay variability and an FO4 chain, which is based on multilevel FO4 metric and circuit-level parameters knobs(i.e., cell topology and driving strength) of the first few cells. We take the slew and load into account to improve the accuracy of this framework. Examples of 28 nm and40 nm digital circuits show that our model conforms with Monte Carlo simulations as well as fabricated chips’ measurements. It is able to model the delay variability effectively to speed up the design process with limited accuracy loss. It also provides a deeper understanding and quick estimation of the path delay variability from the near-threshold to nominal voltages.

关键词： Semiconductor device modeling Monte Carlo methods Temperature Computational modeling Inverters Delays Topology

An efficient path delay variability model for wide-voltage-range digital circuits

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Science China(Information Sciences) 2023年第2期66卷 285-286页

作者： weiwei shan Yuqiang CUI Wentao DAI Xinning LIU Jingjing GUO Peng CAO Jun YANG National ASIC System Engineering Research Center Southeast University Cadence Design Systems Inc. College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications

Dear editor,As process technology advances, the parasitic effects of integrated circuits become increasingly prominent, posing serious challenges for integrated circuit design [1, 2]. Variations in the process corner, voltage, and temperature(PVT) have a more significant impact on path delay in digital circuits in advanced processes, especially at the near-threshold voltage(NTV) [3, 4]. The delay variability of the critical path needs to be evaluated to minimize the timing margin while ensuring reliability. Because NTV circuits have more severe variability than the super-threshold voltage(STV) circuits,

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Morphological and molecular basis of ovarian serous carcinoma

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The Journal of Biomedical Research 2010年第4期24卷 257-263页

作者： Daniel G Rosen Zhihong Zhang weiwei shan Jmsong Liu Department of Pathology the University of Texas M.D. Anderson Cancer Center Houston TX 77030 USA Department of Pathology the First Affiliated Hospital of Nanjing Medical University Nanjing 210029 Jiangsu Province China

Serous carcinoma is the most common type of epithelial ovarian cancer. In this review, we provide a com- prehensive picture of ovarian serous cancers from multiple aspects： the first part of this review summarizes the morphological, histological, and immunological signatures of ovarian serous carcinoma; subsequently, we review the history of the evolvement of different grading systems used in ovarian serous cancer; in the end, we focus on characterizing the genetics that underlie the 2-tiered pathways through which ovarian serous cancers are believed to arise： the low-grade and the high-grade pathways.

关键词： ovarian carcinoma grading morphology molecular genetics tumorigenesis

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Harmonic mixing of Bi_2Sr_2CaCu_2O_(8+x)intrinsic junction at millimeter waveband

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Chinese Science Bulletin 1999年第13期44卷 1191-1194页

作者： XU weiwei, ZHOU Gandong, shan Wenlei, YOU Lixing, YANG Senzu, Jl Zhengming, FENG Yijun, CHENG Qiheng and WU PeihengDepartment of Electronic Science and Engineering , Nanjing University , Nanjing 210093 , China Nanjing University Department of Elecronic Scicncc and Engineering Nanjing China

Using intrinsic Josephson junctions in Ba2Sr2CaCu2O8+x single crystal, harmonic frequency mixing at 8 and 3 mm wavebands was successfully demonstrated at liquid nitrogen temperatures with harmonic numbers up to 68 and 50 respectively. The dependences of intermediate frequency output on the local oscillator power and dc bias were carefully studied.

关键词： Bi2Sr2CaCu2O8+χ intrinsic junction Josephson junction harmonic mixing intermediate frequency output.

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MB15镁合金半固态压缩力学行为研究

特种铸造及有色合金 2005年第11期25卷 667-669页

作者：单巍巍姜巨福罗守靖哈尔滨工业大学

通过MB15镁合金半固态等温压缩试验,研究了半固态材料的力学行为,提出了触变强度是半固态金属在稳态变形过程中触变点的应力,即半固态金属固体骨架所能承受的最大正应力,并分析了加热温度、应变速率、保温时间、固相晶粒大小、晶粒圆整... 详细信息

通过MB15镁合金半固态等温压缩试验,研究了半固态材料的力学行为,提出了触变强度是半固态金属在稳态变形过程中触变点的应力,即半固态金属固体骨架所能承受的最大正应力,并分析了加热温度、应变速率、保温时间、固相晶粒大小、晶粒圆整度及材料本身的强度等因素对半固态触变强度的影响,提出了触变强度的存在条件。结果表明,半固态触变强度随着加热温度的升高、应变速率的降低及保温时间的延长而降低,随着固相晶粒的减小、晶粒圆整度的增加及材料本身强度的增加而增加;当半固态材料内部的固相颗粒相互连结形成固体骨架时,存在触变强度。

关键词： MB15镁合金力学行为触变强度

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