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Leakage Reduction Using DTSCL and Current Mirror SCL Logic Structures for LP-LV Circuits

Circuits and Systems 2013年第1期4卷 20-28页

作者： Sanjeev Rai Ram Awadh Mishra sudarshan tiwari Department of Electronics & Communication Engineering M.N.N.I.T Allahabad India National Institute of Technology Raipur India

This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the performance of these structures with STSCL (Sub-threshold SCL). The first design under consideration is DTPMOS as load device which analyses the performance of Dynamic Threshold SCL (DTSCL) Logic with previous source coupled logic for ultra low power operation. DTSCL circuits exhibit a better power-delay Performance compared with the STSCL Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The second design under consideration uses basic current mirror active load device to provide required voltage swing. Current mirror source coupled logic (CMSCL) can be used for high speed operation. The advantage of this design is that it provides 54% reduction in power delay product over conventional STSCL. The main drawback of this design is that it provides a higher power dissipation compared to other source coupled logic structures. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control over power dissipation. Measurements of test structures simulated in 0.18 μm CMOS technology shows that the proposed DTSCL logic concept can be utilized successfully for bias currents as low as 1 pA. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits. Cadence Virtuoso schematic editor and Spectre Simulation tools have been used.

关键词： CMOS Integrated Circuits CMOS Logic Circuit Dynamic Threshold MOS (DTMOS) Power-Delay Product Source-Coupled Logic (SCL) Sub-Threshold CMOS Sub-Threshold SCL Ultra-Low-Power Circuits Weak Inversion LP-LV(Low Power-Low Voltage)

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New Design Methodologies for High Speed Low-Voltage 1-Bit CMOS Full Adder Circuits

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Computer Technology and Application 2011年第3期2卷 190-198页

作者： Subodh Wairya Rajendra Kumar Nagaria sudarshan tiwari Research Scholar ECED MNNIT Allahabad 211004 India Faculty of ECED MNNIT Allahabad 211004 India

New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.

关键词： Full adder circuits complementary pass-transistor logic (CPL) complementary CMOS high-speed circuits hybrid fulladder XOR-XNOR gate.

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