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SWG: an architecture for sparse weight gradient computation

Science China(Information Sciences) 2024年第2期67卷 302-321页

作者： Weiwei WU Fengbin TU Xiangyu LI Shaojun WEI shouyi yin School of Integrated Circuits Tsinghua University Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology

On-device training for deep neural networks(DNN) has become a trend due to various user preferences and scenarios. The DNN training process consists of three phases, feedforward(FF), backpropagation(BP), and weight gradient(WG) update. WG takes about one-third of the computation in the whole training process. Current training accelerators usually ignore the special computation property of WG and process it in a way similar to FF/BP. Besides, the extensive data sparsity existing in WG, which brings opportunities to save computation, is not well explored. Nevertheless, exploiting the optimization opportunities would meet three underutilization problems, which are caused by(1) the mismatch between WG data dimensions and hardware parallelism,(2) the full sparsity, i.e., the sparsity of feature map(Fmap),error map(Emap), and gradient, and(3) the workload imbalance resulting from irregular sparsity. In this paper, we propose a specific architecture for sparse weight gradient(SWG) computation. The architecture is designed based on hierarchical unrolling and sparsity-aware(HUSA) dataflow to exploit the optimization opportunities of the special computation property and full data sparsity. In HUSA dataflow, the data dimensions are unrolled hierarchically on the hardware architecture. A valid-data trace(VDT) mechanism is embedded in the dataflow to avoid the underutilization caused by the two-sided input sparsity. The gradient is unrolled in PE to alleviate the underutilization induced by output sparsity while maintaining the data reuse opportunities. Besides, we design an intra-and inter-column balancer(IIBLC) to dynamically tackle the workload imbalance problem resulting from the irregular sparsity. Experimental results show that with HUSA dataflow exploiting the full sparsity, SWG achieves a speedup of 12.23× over state-of-the-art gradient computation architecture, Train Ware. SWG helps to improve the energy efficiency of the state-of-the-art training accelerator LNPU from

关键词： CNN training gradient computation sparsity architecture

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Review of chiplet-based design: system architecture and interconnection

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Science China(Information Sciences) 2024年

作者： Yafei LIU Xiangyu LI shouyi yin School of Integrated Circuits Tsinghua University Laboratory of Integrated Circuits and Intelligence Systems Research Institute of Tsinghua University in Shenzhen

Abstract Chiplet-based design, which breaks a system into multiple smaller dice (or “chiplets”) and reassembles them into a new system chip through advanced packaging, has received extensive attention in the post Moore’s law era due to its advantages in terms of cost, performance, and agility. However, significant challenges arise in this implementation approach, including the mapping of functional components onto chiplets, co-optimization of package and architecture, handling the increased latency of communication across functions in different dies, the uncertainty problems of fragment communication subsystems, such as maintaining deadlock-free when independently designed chiplets are combined. Despite various design approaches that attempt to address these challenges, surveying these approaches one-after-another is not the most helpful way to offer a comparative viewpoint. Accordingly, in this paper, we present a more comprehensive and systematic strategy to survey the various approaches. First, we divide them into chiplet-based system architecture design and interconnection design, and further classify them based on different architectures and building blocks of interconnection. Then, we analyze and cross-compare each classification separately, and in addition, we present a topical discussion on the evolution of memory architectures, design automation, and other relevant topics in chiplet-based designs. Finally, some discussions on important topics are presented,emphasizing future needs and challenges in this rapidly evolving field.

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A fast face detection architecture for auto-focus in smart-phones and digital cameras

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Science China Earth Sciences 2016年第12期59卷 175-187页

作者： Peng OUYANG shouyi yin Chenchen DENG Leibo LIU Shaojun WEI Institute of Microelectronic Tsinghua University

Auto-focus is very important for capturing sharp human face centered images in digital and smart phone cameras. With the development of image sensor technology, these cameras support more and more highresolution images to be processed. Currently it is difficult to support fast auto-focus at low power consumption on high-resolution images. This work proposes an efficient architecture for an Ada Boost-based face-priority auto-focus. The architecture supports block-based integral image computation to improve the processing speed on high-resolution images; meanwhile, it is reconfigurable so that it enables the sub-window adaptive cascade classification, which greatly improves the processing speed and reduces power consumption. Experimental results show that 96% detection rate in average and 58 fps(frame per second) detection speed are achieved for the1080p(1920×1080) images. Compared with the state-of-the-art work, the detection speed is greatly improved and power consumption is largely reduced.

关键词： auto-focus AdaBoost face-priority architecture reconfigurable

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维普期刊数据库

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Map Reduce inspired loop mapping for coarse-grained reconfigurable architecture

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Science China(Information Sciences) 2014年第12期57卷 184-197页

作者： yin shouyi SHAO ShengJia LIU LeiBo WEI ShaoJun Institute of Microelectronics Tsinghua University

Our work investigates how to map loops efficiently onto Coarse-Grained Reconfigurable Architecture(CGRA).This paper examines the properties of CGRA and builds Map Reduce inspired models for the loop parallelization *** proposed model has a more detailed performance metric and a more flexible unrolling scheme that can unroll different loop levels with different factors.A Geometric Programming based approach is proposed to resolve the optimization problem of loop parallelization *** proposed approach can find the optimal unrolling factor for each level loop,resulting in better parallelization of *** results show that the proposed approach achieved up to 44%performance gain compared to the state-of-the-art loop mapping scheme.

关键词： reconfigurable computing coarse-grained reconfigurable architecture(CGRA) application mapping loop parallelization Map Reduce

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Architecture, challenges and applications of dynamic reconfigurable computing

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Journal of Semiconductors 2020年第2期41卷 4-13页

作者： Yanan Lu Leibo Liu Jianfeng Zhu shouyi yin Shaojun Wei Institute of Microelectronics Tsinghua University

As a computing paradigm that combines temporal and spatial computations,dynamic reconfigurable computing provides superiorities of flexibility,energy efficiency and area efficiency,attracting interest from both academia and ***,dynamic reconfigurable computing is not yet mature because of several unsolved *** work introduces the concept,architecture,and compilation techniques of dynamic reconfigurable *** also discusses the existing major challenges and points out its potential applications.

关键词： reconfigurable computing architecture challenge application

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维普期刊数据库

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Mixed-Level Modeling Methodology for Network-on-Chip Architecture Exploration

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Chinese Journal of Electronics 2014年第3期23卷 468-473页

作者： yin shouyi ZHANG Zhen HU Yang LIU Leibo WEI Shaojun Institute of Microelectronics Tsinghua University National Laboratory for Information Science and Technology Tsinghua University

As Network on chip(NoC) architecture develops as an solution of interconnection in System on chip(SoC) designs, a detailed and flexible interconnection network model integrated in a full system evaluation framework becomes necessary. In this paper, we first present a mixed abstraction level modeling methodology for the performance evaluation of NoC architecture. Then based on our mixed level modeling methodology, we develop a full system mixed-level NoC evaluation and verification platform. Aiming to explore the details of the performance evaluation and hardware verification of interconnection part, we build NoC router at cycle-accurate, bus cycle level and build SoC peripherals at approximately time, bus phase transaction level which intend to gain higher simulation speed, and lower step to relative development of software. The experimental results show that the mixedlevel NoC evaluation platform can achieve both detailed architecture exploration and fast simulation speed.

关键词： Mixed-level modeling Transaction-level modeling Network-on-Chip SoC design

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Reliability-aware mapping for various No C topologies and routing algorithms under performance constraints

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Science China(Information Sciences) 2015年第8期58卷 168-181页

作者： WU Chen DENG ChenChen LIU LeiBo yin shouyi HAN Jie WEI ShaoJun National Lab for Information Science and Technology Tsinghua University ECE Department University of Alberta

The flexibility of manycore systems to extensive applications is achieved by reconfiguring the interconnections between processing elements(PEs) and the function of PEs. The efficiency of the system is crucially determined by the mapping technique of applications. In this paper, a highly flexible reliability-aware application mapping approach is proposed for manycore network-on-chip(No C) systems. A reliability cost model(RCM) is first presented to measure the reliability cost for a mapping pattern. This model uses the binary number 0/1 to model the reliability cost of each communication path. The overall reliability cost of a mapping pattern is evaluated by taking the cost of each path as a discrete random variable. Based on RCM,a mapping method called reliability cost ratio based branch and bound(RCRBB) is used. With this method,the best mapping among all the possible patterns is found efficiently by discarding those nonoptimal candidate mappings at early stages. The proposed application mapping approach with reliability awareness is applicable to various No C topologies and routing algorithms, while other state-of-the-art approaches on the same topic are only limited to a specific topology and routing algorithm. Even for the same No C architecture, the proposed approach shows significant superiority in many aspects. Experiments show that RCRBB achieves up to 9.07%reliability enhancement on average. Also, it outperforms other approaches in throughput and latency with a relatively low run time.

关键词： reliability-aware network-on-chip(No C) mapping algorithm performance flexibility

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Fast substitution-box evaluation algorithm and its efficient masking scheme for block ciphers

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Science China(Information Sciences) 2021年第8期64卷 262-263页

作者： Hai HUANG Leibo LIU Min ZHU shouyi yin Shaojun WEI Institute of Microelectronics Tsinghua University Harbin University of Science and Technology

Dear editor,Higher-order masking is one of the most effective countermeasures against differential power analysis attacks(DPA) [1]. However, this measure has not yet been widely applied to real-life applications because it suffers from heavy masking-overheads. The efficient realization of non-linear operations, such as substitution-box(S-box), is a major challenge. Among them,

关键词： LUT Fast substitution-box evaluation algorithm and its efficient masking scheme for block ciphers

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An efficient VLSI architecture of speeded-up robust feature extraction for high resolution and high frame rate video

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Science China(Information Sciences) 2013年第7期56卷 136-149页

作者： ZHANG WeiLong LIU LeiBo yin shouyi ZHOU RenYan CAI ShanShan WEI ShaoJun Institute of Micro-Electronics and the National Laboratory for Information Science and Technology Tsinghua University

This paper proposes a VLSI architecture of the optimized Speeded-Up Robust Feature (SURF) algorithm. The SURF algorithm which is widely used in computer vision applications, locates interest points (IPoints) and extracts feature descriptors based on the surrounding gradients. In the proposed approach, the SURF algorithm is modified to make it more suitable for hardware implementation with little accuracy lost compared to OpenSURF, an open source software implementation based on OpenCV. The resource cost and throughput gain are balanced. Word Length Reduction (WLR) is adopted to compress the integral image and reduce the occupied memory resources. The orientations and the feature descriptors of the IPoints are calculated in a more efficient way, which significantly reduces memory accesses. Moreover, the operations are pipelined both in and among the proposed hardware modules. This VLSI architecture has been validated on FPGA (Xilinx Virtex-4 XC4VLX80), which is able to detect IPoints and extract SURF feature descriptors in a VGA (640 × 480) 64 fps video input with a 96 MHz working frequency while dissipating 1.278 W. This throughput is more than double of the ones reported in the latest literatures.

关键词： SURF paralleled VLSI architecture interest point feature extraction WLR

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Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system

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Science China(Information Sciences) 2014年第8期57卷 166-179页

作者： LIU LeiBo CHEN yingJie yin shouyi ZHOU Li YUAN Hang WEI ShaoJun Institute of Microelectronics Tsinghua University Institute of Microelectronics of Chinese Academy of Sciences

In this paper,a TPP(Task-based Parallelization and Pipelining)scheme is proposed to implement AVS(Audio Video coding Standard)video decoding algorithm on REMUS(REconfigurable MUltimedia System),which is a coarse-grained reconfigurable multimedia *** AVS decoder has been implemented with the consideration of HW/SW optimized *** parallel techniques,such as MB(Macro-Block)-based parallel and block-based parallel techniques,and several pipeline techniques,such as MB level pipeline and block level pipeline techniques are adopted by hardware implementation,for performance improvement of the AVS ***,most computation-intensive tasks in AVS video standards,such as MC(Motion Compensation),IP(Intra Prediction),IDCT(Inverse Discrete Cosine Transform),REC(REConstruct)and DF(Deblocking Filter),are performed in the two RPUs(Reconfigurable Processing Units),which are the major computing engines of *** to the proposed scheme,the decoder introduced here can support AVS JP(Jizhun Profile)1920×1088@39fps streams when exploiting a 200 MHz working frequency.

关键词： AVS video decoder coarse-grained reconfigurable multimedia system computation-intensive tasks parallelization and pipelining HW/SW partitioning

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