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Achieving fair service with a hybrid scheduling scheme for CICQ switches

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Science china(Information Sciences) 2012年第3期55卷 689-700页

作者： HU HongChao , GUO YunFei, YI peng & LAN JuLong department of Broadband Information Networks, National digital switching system {3. & technological r&d center (NdSC), zhengzhou 450002, china 1. department of Broadband Information Networks National Digital Switching System Engineering & Technological R&D Center (NDSC) Zhengzhou 450002 China

providing performance guarantees for arriving traffic flows has become an important measure for today’s routing and switching systems. However, none of current scheduling algorithms built on CICQ (combined input and cross-point buffered) switches can provide flow level performance guarantees. Aiming at meeting this requirement, the feasibility of implementing flow level scheduling is discussed thoroughly. Then, based on the discussion, it comes up with a hybrid and stratified fair scheduling (HSFS) scheme, which is hierarchical and hybrid, for CICQ switches. With HSFS, each input port and output port can schedule variable length packets independently with a complexity of O(1). Theoretical analysis show that HSFS can provide delay bound, service rate and fair performance guarantees without speedup. Finally, we implement HSFS in SpES (switch performance evaluation system) to verify the analytical results.

关键词： switching fabric scheduling policy load balancing dynamical re-routing

Achieve load balancing with a dynamic re-routing CICQ switching scheme

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Science china(Information Sciences) 2012年第2期55卷 407-418页

作者： HU HongChao,GUO YunFei,YI peng & LAN JuLong department of Broadband Information Networks,National digital switching system {3. & technological r&d center(NdSC),zhengzhou 450002,china 1. department of Broadband Information Networks National Digital Switching System Engineering & Technological R&D Center (NDSC) Zhengzhou 450002 China

Multi-path based routing and switching can achieve network-wide load balancing and reduce the port conflicts of switching *** by this novel idea,in this paper,through analyzing the feasibility of implementing multi-next-hops in core switching networks comprehensively,we advance a switching scheme called MHrS(multi-next-hop re-routing switch)and a forwarding table management scheme called HMFT(hierarchical multi-stage forwarding table)to support multi-next-hop dynamical *** implements dynamical re-routing in the switches according its congestion status to achieve real-time load balancing,while HMFT can provide traffic with different forwarding paths based on their QoS *** analysis and simulation results show that switches equipped with HMFT and MHrS can provide good delay and throughput ***,they can reduce port conflicts significantly.

关键词： switching fabric scheduling policy load balancing dynamical re-routing

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相依网络的条件依赖群逾渗

物理学报 2019年第7期68卷 302-308页

作者：韩伟涛伊鹏国家数字交换系统工程技术研究中心郑州450000

相依网络鲁棒性研究多集中于满足无反馈条件的一对一依赖,但现实网络节点往往依赖于多节点构成的依赖群,即使群内部分节点失效也不会导致依赖节点失效.针对此现象提出了一种相依网络的条件依赖群逾渗模型,该模型允许依赖群内节点失效比... 详细信息

相依网络鲁棒性研究多集中于满足无反馈条件的一对一依赖,但现实网络节点往往依赖于多节点构成的依赖群,即使群内部分节点失效也不会导致依赖节点失效.针对此现象提出了一种相依网络的条件依赖群逾渗模型,该模型允许依赖群内节点失效比例不超过容忍度γ时,依赖节点仍可正常工作.通过理论分析给出了基于生成函数方法的模型巨分量方程,仿真结果表明方程理论解与相依网络模拟逾渗值相吻合,增大γ值和依赖群规模可提高相依网络鲁棒性.本文模型有助于更好地理解现实网络逾渗现象,对如何增强相依网络鲁棒性有一定指导作用.

关键词：相依网络级联失效逾渗相变

dESIGN ANd EVALUATION OF A pIpELINEd FOrWArdING ENGINE

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Journal of Electronics(china) 2007年第2期24卷 157-162页

作者： Li Yufeng Chen Yue Lan Julong National digital switching system {3. ＆ technological r ＆d center Zhengzhou 450002 China

recent advances in broadband technology have caused forwarding engines to handle pack- ets with over 10 gigabit per second. In this paper, we present a high-speed forwarding pipeline which can finish all of the routing and forwarding tasks in the way of pipelining. We also establish the analysis model of the pipeline with which one can evaluate some key performance parameters of the forwarding engine such as forwarding rate and forwarding delay. We find that the pipeline is of good scalability and can forward unicast packets up to the speed of 40Gbit/s.

关键词： design Forwarding engine pipeline Evaluate

Exploiting Coarse Grain parallelism with parallel recognition Compiler

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Exploiting Coarse Grain Parallelism with Parallel Recognitio...

Semantic Specification Of IA-64 Floating-point Instructions

2006年国际电子、工程及科学领域的分布式计算和应用学术研讨会

作者： Lin Han,Jianmin pang,rongcaiZhao,NingQi National digital switching system {3. &technological r&d center zhengzhou,Henan china

How to analyze serial codes and automatically find its’ parallelism for generating parallel codes to execute on large scale machines is a problem concerned by parallel recognition *** communications between nodes by using message mechanism on distributed memory machines,we need to exploit coarse grain parallelism of serial codes to avoid losing parallel incomings due to expensive communications between computation *** this paper,we present the major compilation passes used in our parallel recognition *** compiler takes a sequential program as input and automatically translates it into parallel code,which can be compiled by the native parallel compiler and run on the target machine.

关键词： parallel recognition compiler parallelization analyses computation and data decomposition code generation

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Semantic Specification Of IA-64 Floating-point Instructions

Automatic Computation and data decomposition Algorithm with No Communication

全国首届数字（虚拟）科技馆技术与应用学术研讨会

作者： Zhang Xuemeng Zhao rongcai pang Jianmin National digital switching system {3. & technological r&d center zhengzhou HeNan 450002 china

The IA-64 floating-point architecture provides performance enhancing features. However,the new features of IA-64 floating-point instructions make it difficult to map the semantics of machine instructions to higher-level intermediate representations,which is the key phase to binary *** paper presents an effective approach to semantic specification of IA-64 floating-point instructions,improving existing technologies according to characteristics of IA-64 floating-point *** particular,the authors take examples for a new algorithm and a few special floating-point instructions used in floating-point programming to describe the details of generating intermediate representation from IA-64 assembly ***,the relevant techniques are evaluated by five programs selected from the SpEC2000Fp benchmarks with a static binary translator from IA-64 to *** can be seen from the preliminary results,the originality and technique soundness of the approach is proved.

关键词： semantic specification floating-point instructions IA-64 binary translation

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Automatic Computation and Data Decomposition Algorithm with ...

prCA： A highly efficient computing architecture

2006年国际电子、工程及科学领域的分布式计算和应用学术研讨会

作者： Han Lin,Zhao rongcai,pang Jianmin,dong Chunli National digital switching system {3. &technological r&d center zhengzhou,Henan china

For distributed memory machines the speed that processor accesses local memories is much faster than its speed to access remote *** how to decompose data and computation properly to achieve maximum parallelism and minimum communication is a key issue of automatic parallel *** this paper,the authors present an automatic decomposition algorithm based on constraint *** the algorithm,a data and computation decomposition result with no communication can be *** releasing these constraint equations,the authors get decomposition result with more *** the result may have communications,so an improved method to eliminate some communications by data replication is also presented.

关键词： parallel recognition compiler computation partition data distribution

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engineering Sciences 2014年第4期12卷 38-47页

作者： Luo Xingguo National digital switching system {3. & technological r&d center Zhengzhou 450002 China

Applications can only reach 8 %~15 % of utilization on modern computer systems. There are many obstacles to improving system efficiency. The key root is the conflict between the fixed general computer architecture and the variable requirements of applications. proactive reconfigurable computing architecture(prCA) is proposed to improve computing efficiency. prCA dynamically constructs an efficient computing architecture for a specific application via reconfigurable technology by perceiving requirements,workload and utilization of computing resources. proactive decision support system(pdSS),hybrid reconfigurable computing array(HrCA) and reconfigurable interconnect(rIC) are intensively researched as the key technologies. The principles of prCA have been verified with four applications on a test bed. It is shown that prCA is feasible and highly efficient.

关键词： prCA efficient computing challenges

dESIGN ANd IMpLEMENTATION OF SINGLE-BUFFErEd rOUTErS

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Journal of Electronics(china) 2007年第4期24卷 470-476页

作者： Hu Ximing Qu Jing Wang Binqiang Wu Jiangxing National digital switching system {3. ＆ technological r＆d center （ NdSC） No. 783 P.O. Box 1001 Zhengzhou 450002 China Institute of Telecommunication engineering Air Force Engineering University No.1 Fenggao Road Xi＇ an 710077 China

A Single-Buffered （SB） router is a router where only one stage of shared buffering is sandwiched between two interconnects in comparison of a Combined Input and Output Queued （CIOQ） router where a central switch fabric is sandwiched between two stages of buffering. The notion of SB routers was firstly proposed by the High-performance Networking Group （HpNG） of Stanford University, along with two promising designs of SB routers： one of which was parallel Shared Memory （pSM） router and the other was distributed Shared Memory （dSM） router. Admittedly, the work of HpNG deserved full credit, but all results presented by them appeared to relay on a Centralized Memory Management Algorithm （CMMA） which was essentially impractical because of the high processing and communication complexity. This paper attempts to make a scalable high-speed SB router completely practical by introducing a fully distributed architecture for managing the shared memory of SB routers. The resulting SB router is called as a Virtual Output and Input Queued （VOIQ） router. Furthermore, the scheme of VOIQ routers can not only eliminate the need for the CMMA scheduler, thus allowing a fully distributed implementation with low processing and commu- nication complexity, but also provide QoS guarantees and efficiently support variable-length packets in this paper. In particular, the results of performance testing and the hardware implementation of our VOIQ-based router （NdSC~ Sr1880-TTM series） are illustrated at the end of this paper. The proposal of this paper is the first distributed scheme of how to design and implement SB routers publicized till now.

关键词： Single-Buffered (SB) router distributed Shared Memory (dSM) parallel Shared Memory (pSM) Virtual Output and Input Queued (VOIQ) NdSC Sr1880-T^TM router