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Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator

Journal of Semiconductors 2014年第9期35卷 97-103页

作者： jitendra kanungo S.Dasgupta Department of Electronics & Communication Engineering Jaypee University of Engineering & Technology Microelectronics & VLSI Group Department of Electronics & Communication Engineering Indian Institute of Technology

We analyze the energy performance of a complete adiabatic circuit/system including the Power Clock Generator （PCG） at the 90 nm CMOS technology node. The energy performance in terms of the conversion efficiency of the PCG is extensively carried out under the variations of supply voltage, process comer and the driver transistor＇s width. We propose an energy-efficient singe cycle control circuit based on the two-stage comparator for the synchronous charge recovery sinusoidal power clock generator （PCG）. The proposed PCG is used to drive the 4-bit adiabatic Ripple Carry Adder （RCA） and their simulation results are compared with the adiabatic RCA driven by the reported PCG. We have also simulated the logically equivalent static CMOS RCA circuit to compare the energy saving of adiabatic and non-adiabatic logic circuits. In the clock frequency range from 25 MHz to 1GHz, the proposed PCG gives a maximum conversion efficiency of 56.48%. This research work shows how the design of an efficient PCG increases the energy saving of adiabatic logic.

关键词： clock-generator energy recovery logic low power single phase sinusoidal clock

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Scaling trends in energy recovery logic:an analytical approach

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Journal of Semiconductors 2013年第8期34卷 79-83页

作者： jitendra kanungo S.Dasgupta Microelectronics & VLSI Group Department of Electronics & Computer EngineeringIndian Institute of Technology

This paper presents an analytical model to study the scaling trends in energy recovery *** energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage,device threshold voltage and gate oxide *** proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the *** research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.

关键词： adiabatic logic energy efficient energy recovery logic low power digital CMOS logic

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