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A 0.13μm CMOS Δ ∑ fractional-N frequency synthesizer for WLAN transceivers

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Journal of Semiconductors 2011年第10期32卷 113-119页

作者：楚晓杰贾海珑林敏石寅代伐 Institute of Semiconductors Chinese Academy of Sciences Department of Electrical and Computer Engineering Auburn University

A fractional-N frequency synthesizer fabricated in a 0.13μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network（WLAN） transceivers.A monolithic LC voltage controlled oscillator（VCO） is implemented with an on-chip symmetric *** fractional-TV frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping（MASH）△Σmodulator with noise-shaped dithering *** results show that in all channels,phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector （PFD） frequency of 20 MHz and a loop bandwidth of 100 *** integrated RMS phase error is no more than 0.8°.The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm^2.

关键词： WLAN IEEE 802.11 b/g frequency synthesizer voltage controlled oscillator △∑modulator

A Low Power Dissipation Wide-Band CMOS Frequency Synthesizer for a Dual-Band GPS Receiver

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Journal of Semiconductors 2008年第10期29卷 1968-1973页

作者：贾海珑任彤林敏陈方雄石寅代伐中国科学院半导体研究所高速电路实验室北京100083 美国Auburn大学电机与计算机工程系

This paper presents a wide tuning range CMOS frequency synthesizer for a dual-band GPS receiver,which has been fabricated in a standard 0.18μm RF CMOS process. With a high Q on-chip inductor, the wide-band VCO shows a tuning range from 2 to 3.6GHz to cover 2.45 and 3.14GHz in case of process corner or temperature variation,with a current consumption varying accordingly from 0.8 to 0.4mA,from a 1.8V supply voltage. Measurement results show that the whole frequency synthesizer consumes very low power of 5.6mW working at L1 band with in-band phase noise less than - 82dBc/Hz and out-of-band phase noise about - ll2dBc/Hz at 1MHz offset from a 3. 142GHz carrier. The performance of the frequency synthesizer meets the requirements of GPS applications very well.

关键词： PLL GPS frequency synthesizer VCO low power CMOS RF

An asymmetric MOSFET-C band-pass filter with on-chip charge pump auto-tuning

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Journal of Semiconductors 2009年第8期30卷 127-131页

作者：陈方略林敏马何平贾海珑石寅代伐 Institute of Semiconductors Chinese Academy of Sciences Suzhou-CAS Semiconductors Integrated Technology Research Center Department of Electrical and Computer Engineering Auburn University

An asymmetric MOSFET-C band-pass filter （BPF） with on chip charge pump auto-tuning is presented. It is implemented in UMC （United Manufacturing Corporation） 0.18 μm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump outputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order low-pass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730-5.340 MHz. The in-band third order harmonic input intercept point （ⅡP3） is 16.621 dBm, with 50Ω as the source impedance. The input referred noise is about 47.455 μVrms. The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm2 and it can be utilized in GPS （global positioning system） and Bluetooth systems.

关键词： MOSFET-C filter auto tuning charge pump CMOS circuit design wireless system

Design of an Active-RC Low-Pass Filter with Accurate Tuning Architecture

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Journal of Semiconductors 2008年第11期29卷 2238-2244页

作者：陈方雄林敏陈备贾海珑石寅代伐中国科学院半导体研究所北京100083 苏州中科半导体集成技术研发中心苏州215021 美国Auburn大学电机与计算机工程系

An active-RC low-pass filter of 5MHz cutoff frequency with a tuning architecture is proposed. It is implemented in 0. 18μm standard CMOS technology. The accuracy of the tuning system is improved to be within （ - 1.24%, ＋ 2.16%） in measurement. The chip area of the tuning system is only a quarter of that of the main-filter. After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The in-band 3rd order harmonic input intercept point （IIP3） is larger than 16. ldBm, with 50Ω as the source impedance. The input referred noise is about 36μVrms The measured group delay variation of the filter between 3 and 5MHz is only 24ns,and the filter power consump- tion is 3.6roW. This filter with the tuning system is realized easily and can be used in many wireless low-IF receiver applications, such as global position systems （GPS）, global system for mobile communications （GSM） and code division multiple access （CDMA） chips.

关键词： CMOS circuit design auto tuning active RC filter wireless system

土右打造全区最大环保煤炭生产加工基地和集散中心 001

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A self-biased PLL with low power and compact area

包头日报

作者：贾海珑

本报讯5月15日，土右旗与中信信通国际物流有限公司签署战略合作框架协议，由中信信通国际物流有限公司投资建设大城西园区环保封闭工程，项目全部建成后，将成为华北地区煤炭物流产业的重要节点、自治区最大的环保煤炭生产加工基地和...

本报讯5月15日，土右旗与中信信通国际物流有限公司签署战略合作框架协议，由中信信通国际物流有限公司投资建设大城西园区环保封闭工程，项目全部建成后，将成为华北地区煤炭物流产业的重要节点、自治区最大的环保煤炭生产加工基地和集散中心。项目规划占地7000亩，拟分

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Journal of Semiconductors 2015年第10期36卷 130-134页

作者：贾海珑陈先敏刘琦冯光涛 Design Service Center Semiconductor Manufacturing International(Shanghai) Corp.

A new low power, low phase jitter, compact realization, and sell-biased PLL, which is fabricated on SMIC 40 nm CMOS technology is introduced. The proposed self-biased PLL eliminates extra band gap biasing circuits, and internally generates all the biasing voltages and currents. Meanwhile, all of the PLL dynamic loop parameters, such as loop bandwidth, natural frequency, damping factors are kept constant adaptively. By optimizing the circuit structures, the perfect unity of chip estate, power dissipation, phase jitter, and loop stability is achieved. THe PLL consumes 4.2 mW of power tinder 1.1 V/2.5 V voltage supply at 2.4 GHz VCO frequency, while occupying a die area of less than 0.02 mmz （180 × 110 μm2）, and the typical period jitter （RMS） is around 2.8 ps.

关键词： self-biased PLL ring VCO low power compact area

A high-performance low-power CMOS AGC for GPS application

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Journal of Semiconductors 2010年第2期31卷 49-53页

作者：雷倩倩许奇明陈治明石寅林敏贾海珑 Department of Applied Electronics Xi'an University of Technology Suzhou-CAS Semiconductors Integrated Technology Research Center

A wide tuning range,low power CMOS automatic gain control（AGC） with a simple architecture is proposed. The proposed AGC is composed of a variable gain amplifier（VGA）,a comparator and a charge pump,and the dB-linear gain is controlled by the charge *** AGC was implemented in a 0.18μm CMOS *** dynamic range of the VGA is more than 55 dB,the bandwidth is 30 MHz,and the gain error is lower than±1.5 dB over the full temperature and gain *** is designed for GPS application and is fed from a single 1.8 V power supply. The AGC power consumption is less than 5 mW,and the area of the AGC is 700×450μm^2.

关键词： linear-in-dB comparator variable gain amplifier automatic gain control

土右旗倾力打造内蒙古西部现代物流集散中心 001

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包头日报

作者：代玉龙贾海珑

现代物流业是一个国家和地区经济运行效率的重要体现，是调整经济结构、转变发展方式的重要手段，是评价一个地区投资环境的重要标准，是企业提高经营管理水平的重要途径。包头市经过近年的快速发展，已成为全国17个区域性物流节点城市...

现代物流业是一个国家和地区经济运行效率的重要体现，是调整经济结构、转变发展方式的重要手段，是评价一个地区投资环境的重要标准，是企业提高经营管理水平的重要途径。包头市经过近年的快速发展，已成为全国17个区域性物流节点城市及全国流通领域现代物流示范城市之一。土?

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纵隔和松果体双病灶生殖细胞肿瘤1例

中华儿科杂志 2025年第1期63卷 87-89页

作者：刘晶赵文王希思金眉陈诚豪贾海威伏利兵于彤苏雁国家儿童医学中心首都医科大学附属北京儿童医院儿童肿瘤中心肿瘤内科儿童肿瘤国家临床重点专科首都医科大学基础-临床联合实验室儿科重大疾病研究教育部重点实验室北京国家儿童医学中心首都医科大学附属北京儿童医院胸外科北京北京右安门医院放疗科北京国家儿童医学中心首都医科大学附属北京儿童医院病理科北京国家儿童医学中心首都医科大学附属北京儿童医院影像中心北京

患儿, 男, 13岁, 因"间断胸痛伴右侧背部、上臂痛2周"就诊。影像学提示前上纵隔和松果体区占位。外周血和脑脊液人绒毛膜促性腺激素均升高。外周血及脑脊液甲胎蛋白正常。纵隔占位病理诊断精原细胞瘤。颅内占位根据影像学特点、血和脑...

患儿, 男, 13岁, 因"间断胸痛伴右侧背部、上臂痛2周"就诊。影像学提示前上纵隔和松果体区占位。外周血和脑脊液人绒毛膜促性腺激素均升高。外周血及脑脊液甲胎蛋白正常。纵隔占位病理诊断精原细胞瘤。颅内占位根据影像学特点、血和脑脊液甲胎蛋白正常、脑脊液人绒毛膜促性腺激素轻度升高临床诊断颅内生殖细胞肿瘤, 生殖细胞瘤可能性大。经化疗、纵隔肿物切除术、纵隔和全脑放疗, 随访11个月完全缓解。

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