VLSI Architecture of EBCOT Tier-2 Encoder for JPEG2000

作     者：Leibo LIU Ning CHEN Li ZHANG Zhihua WANG 

作者单位：Intitute of MicroelectronicsTsinghua University 

会议名称：《2005 6th International Conference on ASIC》

会议日期：2005年

学科分类：080903[工学-微电子学与固体电子学] 0810[工学-信息与通信工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 081001[工学-通信与信息系统] 

关 键 词：Very large scale integration Image coding Tiles Arithmetic Block codes Discrete wavelet transforms Transform coding Rate-distortion CMOS technology Bandwidth 

摘      要：正This paper proposed a VLSI architecture of Embedded Block Coding with Optimized Truncation（EBCOT） Tier-2 encoder for *** on a Rate-Distortion（RD） slope method,the proposed architecture eliminate the iteration of the RD truncation,reduces the scale of the on-chip bit-stream buffering from full tile size down to three-code-block size and at the same time,accurately control the compression bit-rate with 95%*** proposed Tier-2 encoder has already been integrated into the JPEG2000 codec and fabricated with SMIC 0.18um 1P6M CMOS technology.