Designing Power-aware Wrappers for Multi-clock Domain Cores Using Clock Domain Partitioning
作者单位：Graduate School of Information ScienceNara Institute of Science and Technology Kansai Science City630-0192Japan Graduate School of Information ScienceNara Institute of Science and Technology Kansai Science City630-0192Japan The Center For Advanced Computer StudiesUniversity of Louisiana at Lafayette LafayetteLA70504 Graduate School of Information ScienceNara Institute of Science and Technology Kansai Science City630-0192Japan
会议名称：《7th Workshop on RTL and High Level Testing》
会议日期：2006年
学科分类：12[管理学] 1201[管理学-管理科学与工程(可授管理学、工学学位)]
关 键 词：wrapper design multi-clock domain embedded core testing test scheduling
摘 要：正This paper presents a method for designing power-aware test wrappers for embedded cores with multiple clock domains. We make use of partitioning of the clock domains into smaller sub-domains in combination with bandwidth conversion, multiple shift frequencies and gated-clocks to achieve greater flexibility when determining an optimal test schedule under tight power constraints.