Reconfigurable VLSI Architecture for VBSME in MPEG-4 AVC/H.264
作者单位：Microelectronics CenterHarbin Institute of Technology
会议名称：《2005 6th International Conference on ASIC》
会议日期：2005年
学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学]
关 键 词：Very large scale integration MPEG 4 Standard Automatic voltage control Computer architecture Switches CMOS technology Motion estimation Video coding Registers Microelectronics
摘 要：正VBSME is adopted in the MPEG-4 AVC /H.264 *** this paper,we proposed a new reconfigurable VLSI architecture for VBSME with 3 levels of computing complexity to support FS and fast search area sub-sampling ME *** architecture can reuse the smaller blocks’ SADs to calculate 41 motion vectors of a 16X16 block in parallel. Our design was implemented with 0.25um CMOS *** a clock frequency of 52Mhz,the architecture allows the real-time processing of 352x288 （or 720×576） at 30fps with FS（or fast algorithms） in a search range[-16,+15].