Studies on design of micro power consumption E/D NMOS reference source

作     者：Yonggui Hu Gangyi Hu Dongmei Zhu Yun Xu and Jingfeng Yu 1 National Labs of Analog Integrated Circuits Chongqing 400060 China 2 SISC CETC Chongqing 400060 China 

会议名称：《2007 7th International Conference on ASIC Electronic Version(ASICON 2007)》

会议日期：2007年

学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

关 键 词：micro power dissipation E/D NMOS reference depletion-mode N-MOS transistor 

摘      要：In this study,a novel micro power dissipation E/D NMOS reference source circuit was *** circuit is simple in structure,but is *** with a traditional BiCMOS band-gap reference source,the micro power dissipation E/D NMOS reference source has a small static current,and eliminates the need of parasitic bipolar transistor and *** you need to do is to add a depletion-mode N-MONFET process to a conventional P-well process *** E/D NMOS reference source circuit has been developed in 2 μm silicon-gate self-aligned CMOS process *** the range-55 to 125 ℃,the static current measured was less than 2μA,the voltage regulation measured was less than 2mV,and the temperature coefficient measured was less than 100ppm/℃.