An Improved VLSI Implementation Method of FFT Processor
作者单位：Institute of MicroelectronicsSouthwest Jiaotong University Southwest University of Science and Technology
会议名称：《2006 8th International Conference on Signal Processing》
会议日期：2006年
学科分类：080903[工学-微电子学与固体电子学] 0711[理学-系统科学] 0809[工学-电子科学与技术（可授工学、理学学位）] 07[理学] 08[工学] 080401[工学-精密仪器及机械] 0804[工学-仪器科学与技术] 080402[工学-测试计量技术及仪器]
基 金：support by the youth fund of education department of Sichuan province the National Science Foundation of China under Grant No:60371017
摘 要：正An improved VLSI realization of a 1024-dot pipeline FFT processor for handling high speed digital signal has been presented by optimizing the pipeline of complex multiplication and the generation of twiddle factor,The method based on CORDIC algorithm is adopted to achieve a real-time FFT processor and results in a substantial savings in hardware resources and the amount of delay *** is easily implemented in *** processor has been success/idly applied to a Xilinx Virtex- IIxc2v500 chip and obtains the operating clock frequency at 132MHz.