Digit-serial systolic power-sum array in GF(2m)

作     者：Keon-Jik Lee Kee-Won Kim Kee-Young Yoo 

作者单位：Department of Computer EngineeringKyungpook National University 

会议名称：《2001 International Conferences on Info-tech and Info-net》

会议日期：2001年

学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

基　　金：supported by grant No.(2000-2-51200-001-2) from the Basic Research Program of the Korea Science & Engineering Foundation 

关 键 词：finite field power-sum operation digit-serial system systolic array 

摘      要：This paper presents a novel digit-serial-in-serial-out systolic array for performing the power-sum operation C + AB in finite fields GF(2) with the standard basis representation. If the appropriate digit-size is selected,the proposed method can meet the throughput requirement of a specific application with minimum *** the digit size of the regular square form,the latency of the array can be reduced by 20%as before in GF(2). The new digit-serial systolic array with the unidirectional data flow is highly regular, nearest-neighbor connected,and thus well suited for VLSI implementation.