A Sixth-order MASH Algorithm used in ∑-Δ ADC

作     者：Pang Shi-fu, Wang Ji-an, Zhong Zhiqin, Cai Hua, Li Wei, Gong Min (Key lab of microelectronics, of the province, School of Physical Science and Technology Sichuan University, China, 610064) (The College of Micro-electronics and Solid-state Electronics University of Electronic Science and Technology of China, Chengdu, 610054) ( Chengdu Sino microelectronics System Co., ltd. 610041) 

会议名称：《四川省电子学会半导体与集成技术专委会2006年度学术年会》

会议日期：2006年

学科分类：080902[工学-电路与系统] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

关 键 词：Signal Cycle Modulator MASH Over sampling Sigma-Delta ADC Noise-Shaping Converters 

摘      要：In order to improve SNR and decrease over sampling of SDM ADC, higher-order modulator must be used. After detailed analysis on the performance of signal cycle modulator and MASH modulator, different combination of six-order MASH, which has smaller chip area and device number and larger dynamic range (DR), was investigated. It has been shown that MASH(2-2-2)modulator was the most optimized one. The simulation results using the simulink of MATLAB, in this paper, indicted that single bit quantification and three stages MASH (2-2-2) had improves the performance of entire system.