Robust CMOS phase frequency detector for high speed and low jitter charge pump PLL

作     者：周建政 王志功 Zhou Jianzheng;Wang Zhigong

作者机构：东南大学射频与光电集成电路研究所 合肥工业大学计算机与信息学院合肥230009 

出 版 物：《Journal of Southeast University(English Edition)》 (东南大学学报（英文版）)

年 卷 期：2008年第24卷第1期

页      面：15-19页

核心收录：

学科分类：080902[工学-电路与系统] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

主　　题：phase frequency detectors dead-zone blind-zone phase characteristic frequency characteristic 

摘      要：In order to improve the performance of the existing phase frequency detectors （PFDs）, a systematical analysis of the existing PFDs is presented. Based on the circuit architecture, both classifications and comparisons are made. A new robust CMOS phase frequency detector for a high speed and low jitter charge pump phrase-locked loop （PLL） is designed. The proposed PFD consists of two rising-edge triggered dynamic D flip-flops, two positive-edge detectors and delaying units and two OR gates. It adopts two reset mechanisms to avoid the LIP and DN signals to be logic-1 simultaneously. Thus, any current mismatch of the charge pump circuit will not worsen the performance of the PLL. Furthermore, it has hardly any dead-zone phenomenon in phase characteristic. Simulations with ADS are performed based on a TSMC 0. 18-μm CMOS process with a 1.8-V supply voltage. According to the theoretical analyses and simulation results, the proposed PFD shows a satisfactory performance with a high operation frequency （≈ 1 GHz）, a wide phase-detection range [ ± 2π], a near zero dead-zone （ 〈 0. 1 ps）, high reliability, low phase jitter, low power consumption （ ≈100 μW） and small circuit complexity.