A design method for high fabrication tolerance integrated optical mode multiplexer

作     者：Bitao SHEN Haowen SHU Linjie ZHOU Xingjun WANG Bitao SHEN;Haowen SHU;Linjie ZHOU;Xingjun WANG

作者机构：State Key Laboratory on Advanced Optical Communication Systems and Networks Department of ElectronicsSchool of Electronics Engineering and Computer Science Peking University State Key Laboratory of Advanced Optical Communication Systems and NetworksDepartment of Electronic Engineering Shanghai Jiao Tong University Nano-optoelectronics Frontier Center of Ministry of Education Peking University 

出 版 物：《Science China(Information Sciences)》 (中国科学:信息科学(英文版))

年 卷 期：2020年第63卷第6期

页      面：184-194页

核心收录：

学科分类：0810[工学-信息与通信工程] 070207[理学-光学] 0808[工学-电气工程] 07[理学] 0702[理学-物理学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：supported by National Natural Science Foundation of China (Grant Nos. 61635001, 61535002) Major International Cooperation and Exchange Program of the National Natural Science Foundation of China (Grant No. 61120106012) Beijing Municipal Science & Technology Commission (Grant No. Z19110004819006) 

主　　题：mode multiplexer directional coupler taper structure coupled-mode theory genetic algorithm 

摘      要：The tapered asymmetric directional coupler has the potential to realize high fabrication tolerance and high transmission efficiency on-chip mode multiplexer. However, the geometry parameter selection of tapered structure remains empirical. In this paper, we propose a design method for the tapered structure based on genetic algorithm. Combined with the adjusted coupling equations and interpolation method, lowtime-cost optimization can be realized. Three mode multiplexers(TE0&TE1, TE0&TE2 and TE0&TE5)are designed by our method. According to simulation results, the insertion loss of the designed devices is lower than 1.8 dB and the crosstalk is lower than-15 dB when the fabrication error is within required range(±10 nm for TE0&TE2 and TE0&TE5, and ±20 nm for TE0&TE1) in the bandwidth of 1.5–1.6 μm. In addition, the entire optimization process takes only 2 h for each device, which is around the time cost of a single 3 D simulation.