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Metrology Challenges in 3D NAND Flash Technical Development and Manufacturing

作     者:Wei Zhang Jun Xu Sicong Wang Yi Zhou Jian Mi 

作者机构:Yangtze Memory Technologies Co.LtdWuhanChina430000 

出 版 物:《Journal of Microelectronic Manufacturing》 (微电子制造学报(英文))

年 卷 期:2020年第3卷第1期

页      面:9-16页

学科分类:08[工学] 0812[工学-计算机科学与技术(可授工学、理学学位)] 

基  金:The authors would like to thank all YMTC metrology vendors for helping with tool evaluation data collection and data analysis 

主  题:3D NAND Metrology Semiconductor HAR Process Control 

摘      要:3D NAND technical development and manufacturing face many challenges to scale down their devices,and metrology stands out as much more difficult at each *** planar NAND,3D NAND has a three-dimensional vertical structure with high-aspect *** top-down images is not enough for process control,instead inner structure control becomes much more important than before,*** hole ***,multi-layers,special materials and YMTC unique X-Tacking technology also bring other metrology challenges:high wafer bow,stress induced overlay,opaque film *** development can adopt some destructive methodology(TEM,etch-back SEM),while manufacturing can only use nondestructive *** drive some new metrology development,including X-Ray,mass measure and Mid-IR *** 3D NAND suppliers move to150 layers devices,the existing metrology tools will be pushed to the ***,the metrology must innovate.

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