Investigation of gate oxide traps effect on NAND flash memory by TCAD simulation

作     者：He-Kun Zhang Xuan Tian Jun-Peng He Zhe Song Qian-Qian Yu Liang Li Ming Li Lian-Cheng Zhao Li-Ming Gao 章合坤;田璇;何俊鹏;宋哲;蔚倩倩;李靓;李明;赵连城;高立明

作者机构：School of Materials Science and EngineeringShanghai Jiao Tong UniversityShanghai 200240China SanDisk Info Tech ShanghaiShanghai 200241China 

出 版 物：《Chinese Physics B》 (中国物理B（英文版）)

年 卷 期：2020年第29卷第3期

页      面：448-454页

核心收录：

学科分类：08[工学] 0805[工学-材料科学与工程（可授工学、理学学位）] 0704[理学-天文学] 081201[工学-计算机系统结构] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：Project supported by the San Disk Info Tech Shanghai,China the Institute of Microelectronic Materials&Technology,School of Materials Science and Engineering,Shanghai Jiao Tong University,China 

主　　题：NAND flash reliability gate oxide traps trap-assisted tunneling TCAD simulation 

摘      要：The effects of gate oxide traps on gate leakage current and device performance of metal–oxide–nitride–oxide–silicon(MONOS)-structured NAND flash memory are investigated through Sentaurus TCAD. The trap-assisted tunneling(TAT)model is implemented to simulate the leakage current of MONOS-structured memory cell. In this study, trap position, trap density, and trap energy are systematically analyzed for ascertaining their influences on gate leakage current, program/erase speed, and data retention properties. The results show that the traps in blocking layer significantly enhance the gate leakage current and also facilitates the cell program/erase. Trap density ~10^(18) cm^(-3) and trap energy ~ 1 eV in blocking layer can considerably improve cell program/erase speed without deteriorating data retention. The result conduces to understanding the role of gate oxide traps in cell degradation of MONOS-structured NAND flash memory.