Optimization and design of a novel prescaler and its application to GPS receivers
Optimization and design of a novel prescaler and its application to GPS receivers作者机构：1. Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 China2. Hangzhou Zhongke Microelectronics Ltd. Hangzhou 310053 China
出 版 物：《Science China(Information Sciences)》 (中国科学:信息科学(英文版))
年 卷 期：2011年第54卷第9期
页 面：1938-1944页
核心收录：
学科分类：080902[工学-电路与系统] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 080401[工学-精密仪器及机械] 081105[工学-导航、制导与控制] 0804[工学-仪器科学与技术] 0825[工学-航空宇航科学与技术] 0811[工学-控制科学与工程]
基 金：supported by the National High-Tech Research & Development Program of China (Grant No.2007AA12Z344)
主 题：current mode logic (CML) prescaler quadrature local oscillator global positioning system radio-frequency front-end
摘 要：In this work,a novel prescaler based upon new current mode logic (CML) flip-flop architecture applied to global positioning system (GPS) receivers is *** to traditional static current mode logic (CML) flip-flop,it introduces a clock-controlling transistor to reduce the time constant at sensing *** a result,the speed has been maximized and the working range has been *** phase noise of local oscillator (LO) signals coming from the prescaler can be lowered by 6 dB,and the interference of voltage controlled oscillator (VCO) to radio-frequency (RF) front-end apartments (low noise amplifier,mixer,etc.) will be diminished so that the sensitivity of GPS receivers is *** prescaler s maximum input frequency rises up to 6.9 GHz,30% higher than that of traditional architecture,and its power is only 2.16 mW when the supply voltage is 1.8 *** prescaler was manufactured in 0.18-μm CMOS process,and it has been successfully applied to GPS receivers.
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