Implementation of encoder and decoder for LDPC codes based on FPGA

作     者：CHENG Kun SHEN Qi LIAO Shengkai PENG Chengzhi 

作者机构：Department of Modern PhysicsUniversity of Science and Technology of ChinaHefei 230026China Shanghai BranchNational Laboratory for Physical Sciences at Microscale and Department of Modern PhysicsUniversity of Science and Technology of ChinaHefei 230026China Chinese Academy of Sciences Center for Excellence and Synergetic Innovation Center in Quantum Information and Quantum PhysicsUniversity of Science and Technology of ChinaShanghai 201315China 

出 版 物：《Journal of Systems Engineering and Electronics》 (系统工程与电子技术（英文版）)

年 卷 期：2019年第30卷第4期

页      面：642-650页

核心收录：

学科分类：0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

基　　金：supported by the National Natural Science Foundation of China(11705191) the Anhui Provincial Natural Science Foundation(1808085QF180) the Natural Science Foundation of Shanghai(18ZR1443600) 

主　　题：low-density parity-check(LDPC) field programmable gate array(FPGA) normalized min-sum algorithm(NMSA). 

摘      要：This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for *** whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis *** the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.