FPGA IMPLEMENTATION OF RSA PUBLIC-KEY CRYPTOGRAPHIC COPROCESSOR BASED ON SYSTOLIC LINEAR ARRAY ARCHITECTURE
FPGA IMPLEMENTATION OF RSA PUBLIC-KEY CRYPTOGRAPHIC COPROCESSOR BASED ON SYSTOLIC LINEAR ARRAY ARCHITECTURE作者机构：Institute of Electronic Technology The PLA Information EngineeringUniversity Zhengzhou 450004 China
出 版 物：《Journal of Electronics(China)》 (电子科学学刊（英文版）)
年 卷 期：2006年第23卷第5期
页 面：718-722页
学科分类：08[工学] 081202[工学-计算机软件与理论] 0812[工学-计算机科学与技术（可授工学、理学学位）]
主 题：RSA Montgomery's algorithm Systolic linear array Modular multiplication Modular exponentiation
摘 要：In order to make the typical Montgomery’s algorithm suitable for implementation on FPGA, a modified version is proposed and then a high-performance systolic linear array architecture is designed for RSA cryptosystem on the basis of the optimized algorithm. The proposed systolic array architecture has dis- tinctive features, i.e. not only the computation speed is significantly fast but also the hardware overhead is drastically decreased. As a major practical result, the paper shows that it is possible to implement public-key cryptosystem at secure bit lengths on a single commercially available FPGA.
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