FPGA-based hardware-in-the-loop for multi-domain simulation

作     者：Abdelouahab D.Benhamadouche Farid Djahli Adel Ballouti Abdeslem Sahli 

作者机构：Department of ElectronicUniversity Ferhat Abbas Setif 1 Setif 19000Algeria Faculty of TechnologyUniversity Mohamed Boudiaf of M’Sila M’Sila 28000Algeria 

出 版 物：《International Journal of Modeling, Simulation, and Scientific Computing》 (建模、仿真和科学计算国际期刊（英文）)

年 卷 期：2019年第10卷第4期

页      面：20-37页

核心收录：

学科分类：08[工学] 0701[理学-数学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：Hardware-in-the-loop(HIL)simulation multi-domain system verification system control field-programmable gate array(FPGA) VHDL-AMS 

摘      要：In this paper,we present a new approach for complex system design,which allows rapid,efficient and low-cost *** approach can simplify designing tasks and go faster from system modeling to effective hardware *** multi-domain systems requires different engineering competences and several tools,our approach gives a unique design environment,based on the use of VHDL-AMS modeling language and FPGA device within the same design *** approach is intended to enhance hardware-in-the-loop(HIL)practices with a more realistic simulation which improve the verification process in the system design *** paper describes the implementation of a software/hardware platform as a practical support for our approach,the feasibility and the benefits of this approach are demonstrated through a practical case study for power converter *** obtained results show that the developed method achieves significant speed-up compared with conventional simulation,with a minimum used resources and minimum latency.